Overcurrent detection circuit and method, load switch, and portable device

1. An overcurrent detection circuit, comprising:

an enable circuit defining a first enable terminal and a second enable terminal, the second enable terminal distinct from the first enable terminal;

a first overcurrent detection sub-circuit comprising:

a current mirror circuit coupled to an input node of a circuit to be detected, the current mirror circuit configured to generate a mirror current proportional to a first current flowing through the circuit to be detected;

a first comparator having a first input coupled to the current mirror circuit, a second input, an enable input coupled to the first enable terminal, and a first comparison output defining a first overcurrent protection terminal;

a second overcurrent detection sub-circuit comprising:

a second comparator having a first input coupled the second input of the first comparator, a second input, an enable input coupled to the second enable terminal, and a first comparison output defining a second overcurrent protection terminal; and

a reference voltage generation circuit configured to generate and provide a first reference voltage to the second input of the second comparator;

wherein the second comparator is distinct from the first comparator, and the second overcurrent protection terminal is distinct from the first overcurrent protection terminal;

wherein the enable circuit is configured to compare a voltage at an output node of the circuit to be detected with a second reference voltage, to de-assert the second enable terminal and assert the first enable terminal when the voltage at the output node of the circuit to be detected is greater than the second reference voltage, and to de-assert the first enable terminal and assert the second enable terminal when the voltage at the output node of the circuit to be detected is not greater than the second reference voltage;

wherein the first overcurrent detection sub-circuit is configured to perform overcurrent detection on the circuit to be detected in response to assertion of the first enable terminal; and

wherein the second overcurrent detection sub-circuit is configured to perform overcurrent detection on the circuit to be detected in response to assertion of the second enable terminal, and the first and second overcurrent detection sub-circuits configured to assert their respective first and second overcurrent protection terminals to indicate overcurrent on the circuit to be detected.

2. The overcurrent detection circuit according to claim 1 , further comprising a circuit configured to turn off the circuit to be detected in response to detecting assertion of the first or second overcurrent protection terminals.

3. The overcurrent detection circuit according to claim 1 , wherein the circuit to be detected is a switch circuit comprising:

the input node;

the output node;

a first N-channel metal oxide semiconductor (NMOS) switch with a drain coupled to the input node; and

a second NMOS switch with a source coupled to a source of the first NMOS switch and a drain coupled to the output node.

4. The overcurrent detection circuit according to claim 3 , wherein the second overcurrent detection sub-circuit is configured to compare a voltage at the source of the second NMOS switch with the first reference voltage, and to assert the second overcurrent protection terminal in response to the voltage at the source of the second NMOS switch being greater than the first reference voltage.

5. The overcurrent detection circuit according to claim 1 , wherein the reference voltage generation circuit comprises:

a reference current source coupled between the input node and the second input of the second comparator; and

a resistor circuit coupled between the output node and the second input of the second comparator.

6. The overcurrent detection circuit according to claim 3 , wherein the first overcurrent detection sub-circuit comprises:

the second input of the first comparator configured to couple to a third reference voltage during periods of time when the first overcurrent protection terminal is de-asserted, and the second input of the first comparator configured to couple to a fourth reference voltage during periods of time when the first overcurrent protection terminal is asserted, the fourth reference voltage is different than the third reference voltage.

7. An overcurrent detection method, comprising:

causing a first current to flow through a circuit to be detected;

comparing a voltage at an output node of the circuit to be detected with a first reference voltage;

performing overcurrent detection on the circuit to be detected using a first overcurrent detection sub-circuit when the voltage at the output node of the circuit to be detected is greater than the first reference voltage;

asserting, by the first overcurrent detection sub-circuit, a first overcurrent indication terminal when the first overcurrent detection sub-circuit detects overcurrent in the circuit to be detected;

performing overcurrent detection on the circuit to be detected using a second overcurrent detection sub-circuit when the voltage at the output node of the circuit to be detected is not greater than the first reference voltage, the second overcurrent detection sub-circuit is distinct from the first overcurrent detection sub-circuit; and

asserting, by the second overcurrent detection sub-circuit, a second overcurrent indication terminal when the second overcurrent detection sub-circuit detects overcurrent in the circuit to be detected, the second overcurrent indication terminal is distinct from the first overcurrent indication terminal.

8. The overcurrent detection method according to claim 7 , further comprising turning off the circuit to be detected in response to assertion of either the first overcurrent indication terminal or the second overcurrent indication terminal.

9. The overcurrent detection method according to claim 7 , wherein performing overcurrent detection on the circuit to be detected using the second overcurrent detection sub-circuit comprises:

generating a second reference voltage;

comparing a voltage at a first node in the circuit to be detected with the second reference voltage, wherein the voltage at the first node is equal to a product of the first current and a resistance between the output node and the first node plus a voltage at the output node; and

asserting the second overcurrent indication terminal in response to the voltage at the first node being greater than the second reference voltage.

10. The overcurrent detection method according to claim 7

wherein performing overcurrent detection on the circuit to be detected by using the first overcurrent detection sub-circuit comprises:

generating a second current proportional to the first current;

comparing a voltage correlated with the second current with a second reference voltage;

asserting the first overcurrent indication terminal in response to the voltage correlated with the second current being higher than the second reference voltage; and then

de-asserting the first overcurrent indication terminal in response to the voltage correlated with the second current being lower than a third reference voltage.

11. A load switch, comprising:

a switch circuit comprising an input node and an output node;

a first overcurrent detection sub-circuit that is configured to perform overcurrent detection on the switch circuit in response to assertion of a first enable terminal, and to assert a first overcurrent indication terminal by way of a first comparator in response to detecting overcurrent in the switch circuit;

a second overcurrent detection sub-circuit that is configured to perform overcurrent detection on the switch circuit in response to assertion of a second enable terminal, and to assert a second overcurrent indication terminal by a second comparator in response to detecting overcurrent in the switch circuit, the second overcurrent detection sub-circuit distinct from the first overcurrent detection sub-circuit, the second overcurrent indication terminal distinct from the first overcurrent indication terminal, the first enable signal distinct from the second enable signal, and the first comparator distinct from the second comparator; and

an enable circuit configured to compare a voltage at the output node of the switch circuit with a first reference voltage, to assert the first enable terminal when the voltage at the output node of the switch circuit is greater than or equal to the first reference voltage, and to assert the second enable terminal when the voltage at the output node of the switch circuit is not greater than or equal to the first reference voltage.

12. The load switch according to claim 11 , wherein the switch circuit comprises:

a first N-channel metal oxide semiconductor (NMOS) switch with a drain coupled to the input node; and

a second NMOS switch with a source coupled to a source of the first NMOS switch and a drain coupled to the output node,

wherein the second comparator of the second overcurrent detection sub-circuit is configured to compare a voltage at the source of the second NMOS switch with a second reference voltage, and to assert the second overcurrent indication terminal in response to the voltage at the source of the second NMOS switch being greater than the second reference voltage.

13. The load switch according to claim 12 , wherein the second overcurrent detection sub-circuit comprises:

the second comparator having a first input coupled to the source of the second NMOS switch, a second input, and a first comparison output defining the second overcurrent indication terminal; and

a reference voltage generation circuit, configured to generate and provide the second reference voltage to the second input.

14. The load switch according to claim 13 , wherein the reference voltage generation circuit comprises:

a reference current source coupled between the input node and the second input; and

a resistor circuit coupled between the output node and the second input.

15. An electronic device, comprising a load switch comprising:

a switch circuit comprising an input node and an output node;

an enable circuit;

a first overcurrent detection sub-circuit defining a first overcurrent indication terminal, the first overcurrent detection sub-circuit coupled to the enable circuit; and

a second overcurrent detection sub-circuit defining a second overcurrent indication terminal, the second overcurrent detection sub-circuit coupled to the enable circuit, and the second overcurrent detection sub-circuit and the second overcurrent indication terminal distinct from the first overcurrent detection sub-circuit and the first overcurrent indication terminal, respectively;

wherein the enable circuit is configured to compare a voltage at the output node of the switch circuit with a first reference voltage, to assert a first enable terminal to the first overcurrent detection sub-circuit when the voltage at the output node of the switch circuit is greater than the first reference voltage, and to assert a second enable terminal to the second overcurrent detection sub-circuit when the voltage at the output node of the switch circuit is not greater than the first reference voltage;

wherein the first overcurrent detection sub-circuit is configured to perform overcurrent detection on the switch circuit in response to assertion of the first enable terminal, and to assert the first overcurrent indication terminal in response to detecting overcurrent in the switch circuit; and

wherein the second overcurrent detection sub-circuit is configured to perform overcurrent detection on the switch circuit in response to assertion of the second enable terminal, and to assert the second overcurrent indication terminal in response to detecting overcurrent in the switch circuit.

16. The electronic device according to claim 15 , wherein the switch circuit comprises:

a first N-channel metal oxide semiconductor (NMOS) switch with a drain coupled to the input node; and

a second NMOS switch with a source coupled to a source of the first NMOS switch and a drain coupled to the output node,

wherein the second overcurrent detection sub-circuit is configured to compare a voltage at the source of the second NMOS switch with a second reference voltage, and to assert the second overcurrent indication terminal in response to the voltage at the source of the second NMOS switch being greater than the second reference voltage.

17. The electronic device according to claim 16 , wherein the second overcurrent detection sub-circuit comprises:

a first comparator defining a first input coupled to the source of the second NMOS switch, a second input, and a first comparison output defining the second overcurrent indication terminal; and

a reference voltage generation circuit configured to generate and provide the second reference voltage to the second input.

18. The electronic device according to claim 17 , wherein the reference voltage generation circuit comprises:

a reference current source coupled between the input node and the second input; and

a resistor circuit coupled between the output node and the second input.

19. The electronic device according to claim 17 , wherein the first overcurrent detection sub-circuit comprises:

a second comparator having a first input, a second input, and a first comparison output defining the first overcurrent indication terminal;

the second input of the second comparator coupled to a third reference voltage during periods of time when the first overcurrent indication terminal is de-asserted, and the second input of the second comparator coupled to a fourth reference voltage during periods of time when the first overcurrent indication terminal is asserted, the third reference voltage different than the fourth reference voltage; and

a current mirror circuit coupled to the first input of the second comparator, and configured to generate a second current proportional to a first current flowing through the switch circuit and to provide a voltage correlated with the second current to the first input of the second comparator.