Method and apparatus for proper recognition of overload condition in a power device
Disclosed herein is circuitry for protecting a power supply system from overcurrent conditions by monitoring an input voltage and an output voltage of the power supply system, detecting an overcurrent condition based on the monitored input and output voltages, and determining whether the overcurrent condition is caused by an input transient or an output short circuit. When the detected overcurrent condition is caused by an input transient, a gate of a power transistor is controlled to maintain current flow to a load. When the detected overcurrent condition is caused by an output short circuit, the power transistor is turned off to protect the power supply system.
1 . A power supply system, comprising:
a power transistor having a first conduction terminal coupled to an input node configured to receive an input voltage, a second conduction terminal coupled to an output node configured to generate an output voltage, and a control terminal configured to receive a gate control signal;
a first shut-down transistor having a first conduction terminal coupled to the control terminal of the power transistor, a second conduction terminal coupled to ground, and a control terminal configured to receive a shut down signal;
a second shut-down transistor having a first conduction terminal coupled to the control terminal of the power transistor, a second conduction terminal coupled to the output node, and a control terminal;
a current source configured to source current to the control terminal of the power transistor in response to assertion of a pullup boost signal;
a power detector configured to assert a power-good flag when a voltage across the current source is at a minimum threshold;
a gate-to-source voltage detector configured to assert a low gate-to-source voltage flag when a gate-to-source voltage of the power transistor is below a gate-to-source threshold;
an overcurrent detector configured to assert an overcurrent protection flag based upon sensing an output current sourced by the power transistor to the output node;
an output voltage drop detector configured to assert an output voltage drop flag when the output voltage has fallen below a sampled output voltage by an offset;
a first logic circuit having a first input coupled to receive the output voltage drop flag, a second input coupled to receive a sensed output voltage flag, and an output;
a fault indication circuit configured to assert the shut down signal in response to assertion of the output of the first logic circuit;
a gate control circuit configured to generate the gate control signal as being asserted when the shut down signal is deasserted but as being deasserted when the shut down signal is asserted;
a state machine configured to generate the pullup boost signal, a gate-to-source switch signal, and a sensed output voltage flag based upon the low gate-to-source voltage flag, the power-good flag, and the overcurrent protection flag; and
a second logic circuit having a first input coupled to receive the gate-to-source switch signal, a second input coupled to receive the shut down signal, and an output coupled to the control terminal of second shut-down transistor.
2 . The power supply system of claim 1 , wherein the state machine comprises:
a third logic circuit having a first input receiving the power-good flag, a second input receiving the pullup boost signal, and an output;
a fourth logic circuit having a first input receiving the output of the third logic circuit, a second input receiving the shut down signal, and an output;
a first flip flop having a data input coupled to ground, a clock input coupled to the low gate-to-source voltage flag, a reset input coupled to the output of the fourth logic circuit, a set input, a non-inverting data output, and an inverting data output;
a second flip flop having a data input coupled to a supply voltage node, a clock input coupled to the non-inverting data output of the first flip flop, a reset input coupled to the output of the fourth logic circuit, a non-inverting data output at which the pullup boost signal is generated, and an inverting data output;
a fifth logic circuit having a first input receiving the overcurrent protection flag, a second input receiving the inverting data output of the first flip flop, and an output coupled to the set input of the first flip flop;
a sixth logic circuit having a first input coupled to the non-inverting data output of the first flip flop, a second input coupled to the non-inverting data output of the second flip flop, and an output at which the sensed output voltage flag is produced; and
a seventh logic circuit gate having a first input coupled to the non-inverting data output of the first flip flop, a second input coupled to the inverting data output of the second flip flop, and an output at which the gate-to-source switch signal is generated.
3 . The power supply system of claim 1 , wherein the first logic circuit is a first AND gate and the second logic circuit is a first OR gate.
4 . The power supply system of claim 3 , wherein the state machine comprises:
a third AND gate having a first input receiving the power-good flag, a second input receiving the pullup boost signal, and an output;
a second OR gate having a first input receiving the output of the third AND gate, a second input receiving the shut down signal, and an output;
a first flip flop having a data input coupled to ground, a clock input coupled to the low gate-to-source voltage flag, a reset input coupled to the output of the second OR gate, a set input, a non-inverting data output, and an inverting data output;
a second flip flop having a data input coupled to a supply voltage node, a clock input coupled to the non-inverting data output of the first flip flop, a reset input coupled to the output of the second OR gate, a non-inverting data output at which the pullup boost signal is generated, and an inverting data output;
a second AND gate having a first input receiving the overcurrent protection flag, a second input receiving the inverting data output of the first flip flop, and an output coupled to the set input of the first flip flop;
a third OR gate having a first input coupled to the non-inverting data output of the first flip flop, a second input coupled to the non-inverting data output of the second flip flop, and an output at which the sensed output voltage flag is produced; and
a fourth AND gate having a first input coupled to the non-inverting data output of the first flip flop, a second input coupled to the inverting data output of the second flip flop, and an output at which the gate-to-source switch signal is generated.
5 . The power supply system of claim 1 , wherein the output voltage drop detector comprises:
a comparator having an inverting input terminal coupled to receive a representative voltage equal to the output voltage plus an offset voltage, a non-inverting input terminal, and an output terminal at which the output voltage drop flag is generated;
a sampling capacitor coupled between the non-inverting input terminal of the comparator and ground, the sampling capacitor configured to store the sampled output voltage; and
a sampling transistor configured to selectively couple the output voltage to the non-inverting input terminal of the comparator, based upon the sensed output voltage flag.
6 . The power supply system of claim 1 , wherein the output voltage drop detector comprises:
a voltage dividing ladder coupled between the output voltage and ground, with a scaled version of the output voltage formed at a first node, the first node being a tap of the voltage dividing ladder;
a buffer coupled between the first node and a second node;
a resistance coupled between the second node and a third node;
a current source configured to source a constant current to the third node;
a comparator having an inverting input terminal coupled to the third node, a non-inverting input terminal coupled to a fourth node, and an output at which the output voltage drop flag is generated;
a sampling capacitor coupled between the fourth node and ground; and
a sampling transistor configured to selectively couple the second node to the fourth node, based upon the sensed output voltage flag.
7 . A method for distinguishing between overcurrent conditions in a power supply system, the method comprising:
detecting an overcurrent condition and asserting an overcurrent protection flag;
asserting a sensed output voltage signal and a gate-to-source switch signal to discharge a gate of a power transistor;
detecting a gate-to-source voltage of the power transistor below a threshold and asserting a gate-to-source voltage low flag;
charging the gate of the power transistor in response to the gate-to-source voltage low flag;
detecting a drop in output voltage while the sensed output voltage signal is asserted and asserting an output voltage drop flag; and
shutting down the power transistor if the output voltage drop flag is asserted while the sensed output voltage signal is asserted.
8 . The method of claim 7 , further comprising:
resetting the sensed output voltage signal and the gate-to-source switch signal if the overcurrent condition ends and the gate-to-source voltage rises above the threshold before the output voltage drop flag is asserted.
9 . The method of claim 7 , wherein detecting the drop in output voltage comprises:
holding a previous value of the output voltage when the sensed output voltage signal is deasserted;
comparing a current value of the output voltage plus an offset to the held previous value; and
asserting the output voltage drop flag if the current value plus the offset drops below the held previous value.
10 . The method of claim 7 , wherein detecting the drop in output voltage comprises:
generating a scaled version of the output voltage;
holding a previous value of the scaled version of the output voltage when the sensed output voltage signal is deasserted;
generating a comparison voltage from the scaled version of the output voltage and a current source; and
asserting the output voltage drop flag if the comparison voltage drops below the held previous value.
11 . The method of claim 7 , wherein asserting the sensed output voltage signal and the gate-to-source switch signal comprises:
setting a first flip flop in response to the overcurrent protection flag being asserted;
asserting the sensed output voltage signal in response to an output of the first flip flop being asserted; and
asserting the gate-to-source switch signal in response to the output of the first flip flop and an inverted output of a second flip flop being asserted.
12 . The method of claim 11 , wherein charging the gate comprises:
setting the second flip flop in response to the gate-to-source voltage low flag being asserted; and
enabling a current source to charge the gate in response to an output of the second flip flop being asserted.