Semiconductor interconnect structure having a graphene barrier layer
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.
1. A method for forming a semiconductor structure, the method comprising:
forming a dielectric layer over a metal layer;
forming an opening in the dielectric layer, wherein the opening exposes surfaces of the dielectric layer and a top surface of the metal layer;
forming a self-assembly monolayer (SAM) on the exposed surfaces of the dielectric layer;
performing an anneal process on the SAM to form a graphene barrier layer; and
filling the opening with a conductor material, wherein the conductor material is in contact with the graphene barrier layer and the top surface of the metal layer.
2. The method of claim 1 , wherein forming the opening comprises forming via and trench structures in the dielectric layer, and wherein the SAM is formed in the via and trench structures.
3. The method of claim 1 , wherein the SAM is formed using a chemical vapor deposition (CVD), a plasma-enhanced CVD (PECVD), an atomic laser deposition (ALD), or a plasma-enhanced ALD (PEALD).
4. The method of claim 1 , wherein the SAM is formed at a temperature between about room temperature and about 450° C.
5. The method of claim 1 , wherein the anneal process is performed at a temperature between about 200° C. and about 450° C.
6. The method of claim 1 , wherein the anneal process is performed for about 600 s.
7. The method of claim 1 , wherein the anneal process comprises a three-step anneal process comprising first, second, and third anneal operations performed at about 200° C., about 300° C., and about 400° C., respectively.
8. The method of claim 7 , wherein the first, second, and third anneal operations are performed for about 300 s, about 600 s, and about 60 s, respectively.
9. The method of claim 1 , wherein filling the opening with the conductor material comprises depositing a first conductor material on the top surface of the metal layer and depositing a second conductor material on the first conductor material and the graphene barrier layer.
10. The method of claim 1 , wherein the SAM comprises a head group comprising an organosulfur compound and a terminal end comprising alkyl groups.
11. A method for forming a semiconductor structure, the method comprising:
forming a substrate;
forming a metal layer on the substrate;
forming a dielectric layer over the metal layer, the dielectric layer comprising an opening that exposes a portion of the metal layer;
depositing a self-assembly monolayer (SAM) on side surfaces of the dielectric layer in the opening;
performing an anneal process on the SAM, wherein the anneal process converts the SAM to a graphene barrier layer; and
depositing a conductor material on the exposed portion of the metal layer, wherein at least a portion of the graphene barrier layer is between the conductive layer and the dielectric layer.
12. The method of claim 11 , wherein depositing the SAM comprises depositing a SAM material at a temperature between about room temperature and about 450° C.
13. The method of claim 11 , wherein the anneal process is performed at a temperature between about 200° C. and about 450° C.
14. The method of claim 11 , wherein the anneal process comprises a three-step anneal process comprising first, second, and third anneal operations performed at about 200° C., about 300° C., and about 400° C., respectively.
15. The method of claim 14 , wherein the first, second and third anneal operations are performed for about 300 s, about 600 s, and about 60 s, respectively.
16. The method of claim 11 , wherein filling the opening with the conductor material comprises depositing a first conductor material on the top surface of the metal layer and depositing a second conductor material on the first conductor material and the graphene barrier layer.
17. A method for forming a semiconductor structure, the method comprising:
forming a conductive interconnect layer;
forming a dielectric layer over the conductive interconnect layer, the dielectric layer comprising an opening that exposes a portion of the conductive interconnect layer;
depositing a self-assembly monolayer (SAM) on side surfaces of the dielectric layer in the opening;
performing an anneal process on the SAM to form a graphene barrier layer; and
depositing a first conductive layer on the exposed portion of the conductive interconnect layer, wherein the graphene barrier layer is between the first conductive layer and the dielectric layer; and
depositing a second conductive layer on the first conductive layer, wherein the graphene barrier layer is between the second conductive layer and the dielectric layer.
18. The method of claim 17 , wherein depositing the SAM comprises depositing a SAM material at a temperature between about room temperature and about 450° C.
19. The method of claim 17 , wherein the anneal process is performed at a temperature between about 200° C. and about 450° C.
20. The method of claim 17 , wherein the anneal process comprises a three-step anneal process comprising first, second, and third anneal operations performed at about 200° C., about 300° C., and about 400° C., respectively.