IP Library Granted Patent US 12,456,650
Granted Patent B2
US 12,456,650 · App. 17/991,090 · Granted Oct 28, 2025

Semiconductor device and method for manufacturing the same

Inventors: Kyung Wook Kim (Hwaseong-si, KR); Seung Yong Yoo (Incheon, KR); Eui Bok Lee (Seoul, KR); Jin Nam Kim (Anyang-si, KR); Eun-Ji Jung (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L21/76844H01L21/76846H01L21/76865H01L21/76895H01L23/535
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Quick Facts
Patent No.
US 12,456,650
App. No.
17/991,090
Granted
Oct 28, 2025
Kind
B2
Abstract

A semiconductor device is provided. The semiconductor device includes: a lower line structure; an upper interlayer insulating film provided on the lower line structure and having a trench formed therein, wherein the trench includes a wiring line trench and a via trench extending from the wiring line trench to the lower line structure; and an upper line structure provided in the line trench, wherein the upper line structure includes an upper barrier film and an upper filling film. The upper filling film includes a first sub-filling film in contact with the upper interlayer insulating film, and a second sub-filling film provided on the first sub-filling film. The first sub-filling film fills an entirety of the upper via trench and covers at least a portion of a bottom surface of the upper wiring line trench.

Claims (49)

1. A semiconductor device comprising:

a lower line structure;

an upper interlayer insulating film provided on the lower line structure and having an upper line trench formed therein, wherein the upper line trench comprises an upper wiring line trench and an upper via trench extending from the upper wiring line trench to the lower line structure; and

an upper line structure provided in the upper line trench, wherein the upper line structure comprises an upper barrier film and an upper filling film,

wherein the upper filling film comprises a first sub-filling film in contact with the upper interlayer insulating film, and a second sub-filling film provided on the first sub-filling film,

wherein the first sub-filling film is a single film which fills an entirety of the upper via trench, covers at least a portion of a bottom surface of the upper wiring line trench, and extends between the upper interlayer insulating film and the upper barrier film to a sidewall of the upper line trench, and

wherein the upper barrier film is in contact with the upper interlayer insulating film, and is provided between the second sub-filling film and the upper interlayer insulating film.

2. The semiconductor device of claim 1 , wherein the upper barrier film extends along and on at least a portion of the sidewall of the upper wiring line trench.

3. The semiconductor device of claim 2 , wherein the bottom surface of the upper wiring line trench comprises a first area and a second area,

wherein the first sub-filling film covers the first area of the bottom surface of the upper wiring line trench, and

wherein the upper barrier film covers the second area of the bottom surface of the upper wiring line trench.

4. The semiconductor device of claim 1 , wherein the first sub-filling film covers an entirety of the bottom surface of the upper wiring line trench.

5. The semiconductor device of claim 1 , wherein an upper surface of the first sub-filling film and a bottom surface of the second sub-filling film are in contact with each other.

6. The semiconductor device of claim 1 , further comprising an upper liner provided between the upper barrier film and the second sub-filling film.

7. The semiconductor device of claim 6 , wherein the upper liner comprises a first sub-liner and a second sub-liner sequentially provided on the upper barrier film, and

wherein each of the first sub-liner and the second sub-liner extends along a bottom surface of the second sub-filling film.

8. The semiconductor device of claim 6 , wherein the upper liner comprises a first sub-liner and a second sub-liner sequentially provided on the upper barrier film,

wherein the first sub-liner does not extend along and on a bottom surface of the second sub-filling film,

wherein the second sub-liner extends along and on the bottom surface of the second sub-filling film.

9. The semiconductor device of claim 6 , wherein the upper liner comprises any one or any combination of cobalt (Co) and ruthenium (Ru).

10. The semiconductor device of claim 1 , wherein the first sub-filling film and the second sub-filling film comprise different materials.

11. The semiconductor device of claim 1 , wherein the lower line structure comprises a lower filling film and a lower capping film provided on the lower filling film, and

wherein the first sub-filling film is in contact with an upper surface of the lower capping film.

12. The semiconductor device of claim 1 , wherein the lower line structure comprises a lower filling film and a lower capping film provided on the lower filling film,

wherein an upper surface of the lower filling film comprises a first area on which the lower capping film is provided, and a second area on which the lower capping film is not provided, and

wherein the upper line structure is in contact with the second area.

13. A semiconductor device comprising:

a lower line structure;

an upper interlayer insulating film provided on the lower line structure and having an upper line trench formed therein, wherein the upper line trench comprises an upper wiring line trench and an upper via trench extending from the upper wiring line trench to the lower line structure; and

an upper line structure is provided in the upper line trench, wherein the upper line structure comprises an upper barrier film and an upper filling film,

wherein the upper filling film comprises a first sub-filling film, and a second sub-filling film provided on the first sub-filling film,

wherein the first sub-filling film is a single film which fills an entirety of the upper via trench, covers at least a portion of a bottom surface of the upper wiring line trench, and extends between the upper interlayer insulating film and the upper barrier film to a sidewall of the upper line trench, and

wherein the upper barrier film extends along and on at least a portion of the sidewall of the upper wiring line trench, and the second sub-filling film is provided between portions of the upper barrier film on an upper surface of the first sub-filling film.

14. The semiconductor device of claim 13 , wherein the upper barrier film is in contact with the upper interlayer insulating film and extends along a portion of the sidewall of the upper wiring line trench.

15. The semiconductor device of claim 13 , wherein the first sub-filling film and the second sub-filling film are in contact with each other.

16. The semiconductor device of claim 13 , further comprising a first upper liner and a second upper liner provided between the upper barrier film and the second sub-filling film,

wherein at least one of the first upper liner and the second upper liner extends along a bottom surface of the second sub-filling film.

17. The semiconductor device of claim 13 further comprising an upper liner provided between the upper barrier film and the second sub-filling film,

wherein a bottom surface of the second sub-filling film extends between portions of the upper liner.

18. A semiconductor device comprising:

a lower line structure;

an upper interlayer insulating film provided on the lower line structure and having an upper line trench formed therein, wherein the upper line trench comprises an upper wiring line trench and an upper via trench extending from the upper wiring line trench to the lower line structure; and

an upper line structure provided in the upper line trench, wherein the upper line structure comprises an upper barrier film, an upper liner, and an upper filling film,

wherein the upper filling film comprises a first sub-filling film and a second sub-filling film provided on the first sub-filling film,

wherein the first sub-filling film is a single film which fills an entirety of the upper via trench and a portion of the upper wiring line trench, and extends between the upper interlayer insulating film and the upper barrier film to a sidewall of the upper line trench,

wherein the upper barrier film is in contact with the upper interlayer insulating film and extends along and on a portion of the sidewall of the upper wiring line trench, and

wherein the upper liner is provided between the upper barrier film and the second sub-filling film.

19. The semiconductor device of claim 18 , wherein the first sub-filling film and the second sub-filling film are in contact with each other.

20. The semiconductor device of claim 18 , wherein the upper liner extends along a bottom surface of the second sub-filling film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2022
From: KIM, KYUNG WOOK; YOO, SEUNG YONG; LEE, EUI BOK; KIM, JIN NAM; JUNG, EUN-JI
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061841/0696 →
Priority Claims (1)
KR 10-2022-0002448 · Jan 7, 2022 · national
Continuity (1)
Related Publication 20230282512A1 · Sep 7, 2023
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