Three-dimensional memory devices and fabricating methods thereof
Embodiments of 3D memory structures and methods for forming the same are disclosed. A method for forming a three-dimensional (3D) memory structure includes forming a dielectric layer on a substrate and forming a first plurality of openings in the dielectric layer at a staircase region of the 3D memory structure. The method also includes forming a second plurality of openings in the dielectric layer at a peripheral device region of the 3D memory structure and forming at least one hard mask layer in the first plurality of openings of the staircase region and in the second plurality of openings of the peripheral device region. The method further includes etching the dielectric layer using the at least one hard mask layer to form first and second pluralities of via extension regions in top portions of the respective first and second pluralities of openings. The method further includes disposing a first conductive material in the first and second pluralities of openings to form respective first and second pluralities of contact wires. The method also includes disposing a second conductive material in the first and second pluralities of via extension regions to form first and second pluralities of contact pads and forming first and second pluralities of lead wires on the first and second pluralities of contact pads, respectively.
1. A method for forming a three-dimensional (3D) memory structure, the method comprising:
forming a dielectric layer on a substrate;
forming a first plurality of openings in the dielectric layer at a staircase region of the 3D memory structure;
forming a second plurality of openings in the dielectric layer at a peripheral device region of the 3D memory structure;
forming at least one hard mask layer in the first plurality of openings of the staircase region and in the second plurality of openings of the peripheral device region;
etching the dielectric layer using the at least one hard mask layer to form first and second pluralities of via extension regions in top portions of the respective first and second pluralities of openings;
disposing a first conductive material in the first and second pluralities of openings to form respective first and second pluralities of contact wires;
disposing a second conductive material in the first and second pluralities of via extension regions to form first and second pluralities of contact pads; and
forming first and second pluralities of lead wires on the first and second pluralities of contact pads, respectively.
2. The method of claim 1 , wherein the forming the at least one hard mask layer comprises disposing a second hard mask layer on a first hard mask layer.
3. The method of claim 2 , wherein the disposing the first hard mask layer comprises disposing the first hard mask layer in the first and second pluralities of openings.
4. The method of claim 2 , wherein the forming the at least one hard mask layer further comprises performing a planarization process on the first hard mask layer.
5. The method of claim 2 , wherein the disposing the first hard mask layer comprises disposing an amorphous carbon layer.
6. The method of claim 2 , wherein the disposing the second hard mask layer comprises disposing a silicon oxynitride layer.
7. The method of claim 1 , further comprising performing a planarization process on the first and second pluralities of contact pads such that top surfaces of the dielectric layer and the first and second pluralities of contact pads are substantially level.
8. The method of claim 1 , further comprising removing the at least one hard mask layer.
9. The method of claim 1 , wherein the forming the first and second pluralities of lead wires comprises aligning each lead wire of the first and second pluralities of lead wires to a corresponding contact pad of the first and second pluralities of contact pads.
10. The method of claim 1 , wherein the forming the first plurality of openings in the staircase region comprises etching the dielectric layer until an underlying conductive layer is exposed.
11. The method of claim 1 , wherein the forming the second plurality of openings in the peripheral device region comprises etching the dielectric layer until a doped region of a transistor is exposed.
12. A method for forming a three-dimensional (3D) memory structure, the method comprising:
forming a dielectric layer on a substrate;
etching the dielectric layer to form a first plurality of openings in a staircase region of the 3D memory structure;
etching the dielectric layer to form a second plurality of openings in a peripheral device region of the 3D memory structure;
disposing a first hard mask layer in the first and second pluralities of openings and on a top surface of the dielectric layer;
disposing a second hard mask layer on the first hard mask layer;
etching the dielectric layer using the first and second hard mask layers to form first and second pluralities of via extension regions in top portions of the respective first and second pluralities of openings;
disposing a conductive material in the first and second pluralities of via extension regions to form first and second pluralities of contact pads, respectively; and
forming first and second pluralities of lead wires on the first and second pluralities of contact pads, respectively.
13. The method of claim 12 , wherein disposing the first hard mask layer comprises performing a planarization process on the first hard mask layer.
14. The method of claim 12 , wherein the disposing the first hard mask layer comprises disposing an amorphous carbon layer.
15. The method of claim 12 , wherein the disposing the second hard mask layer comprises disposing a silicon oxynitride material.
16. A 3D NAND memory structure, comprising:
a substrate having a dielectric layer formed thereon;
a staircase region comprising an alternating conductor/dielectric layer stack formed in the dielectric layer;
a peripheral device region comprising a peripheral device; and
a plurality of interconnect structures, comprising:
a first plurality of conductive structures in the staircase region, comprising a first plurality of contact pads and a first plurality of contact wires, wherein each contact wire is electrically coupled to a conductive layer of the alternating conductive/dielectric layer stack; and
a second plurality of conductive structures in the peripheral device region, comprising a second plurality of contact pads and a second plurality of contact wires, wherein each contact wire is electrically coupled to one or more terminals of the peripheral device; and
first and second pluralities of lead wires respectively on the first and second pluralities of contact pads.
17. The 3D NAND memory structure of claim 16 , wherein each contact pad of the first plurality of contact pads is formed in a top portion of each contact wire of the first plurality of contact wires.
18. The 3D NAND memory structure of claim 16 , wherein each contact pad of the second plurality of contact pads is formed in a top portion of each contact wire of the second plurality of contact wires.
19. The 3D NAND memory structure of claim 16 , wherein a width of each contact pad of the first pluralities of contact pads can be in a range between about 0.3 μm and about 0.6 μm.
20. The 3D NAND memory structure of claim 16 , wherein a thickness of each contact pad of the first or second pluralities of contact pads can be in a range between about 0.05 μm and about 0.1 μm.