Fault-tolerant power-driven synthesis

1. A method comprising:

modeling power consumption of spike communication in a neurosynaptic network as weighted wire length, the neurosynaptic network comprising a plurality of physical neurosynaptic cores interconnected by a plurality of routers, the weighted wire length being weighted by spike frequency among the plurality of physical neurosynaptic cores, the weighted wire length being proportional to a sum of a number of intra-chip hops that each spike travels and an inter-chip hop length, wherein the weighted wire length, P, is determined by the equation:

P =Σ e∈E w ( e )( E h h ( e )+ E v v ( e ))+Σ e:k i ≠k j w ( e ) H p E p ,

wherein e corresponds to an edge in a core, w corresponds to a weight of edge e, E h corresponds to power consumed for a hop of a spike sent in a horizontal distance, h corresponds to a horizontal distance of edge e, E v corresponds to power consumed for a hop of a spike sent in a vertical distance, v corresponds to a vertical distance of edge e, H p corresponds to the inter-chip hop length, E p corresponds to power consumed when a spike travels across a chip boundary, and k i corresponds to a chip index;

locating at least one faulty core of the plurality of physical neurosynaptic cores;

modeling a placement blockage at the location of the at least one faulty core;

determining a placement of a plurality of logical cores on the physical neurosynaptic cores by minimizing the weighted wire length, the placement minimizing power consumption of the spike communication while avoiding the faulty core; and

configuring the physical neurosynaptic cores to execute the plurality of logical cores according to the determined placement.

2. The method of claim 1 , wherein the minimizing the weighted wire length comprises applying a VLSI placement algorithm.

3. The method of claim 2 , wherein the VLSI placement algorithm comprises partitioning-based placement.

4. The method of claim 1 , further comprising:

locating at least one faulty router of the plurality of routers; and

modeling a second placement blockage, the second placement blockage including at least a core of the plurality of cores associated with the faulty router.

5. The method of claim 1 , wherein the plurality of neurosynaptic cores is divided among a plurality of chips.

6. A method comprising:

modeling power consumption of spike communication in a neurosynaptic network as weighted wire length, the neurosynaptic network comprising a plurality of physical neurosynaptic cores interconnected by a plurality of routers, the weighted wire length being weighted by spike frequency among the plurality of physical neurosynaptic cores, the weighted wire length being proportional to a sum of a number of intra-chip hops that each spike travels and an inter-chip hop length, wherein the weighted wire length, P, is determined by the equation:

P =Σ e ∈E w ( e )( E h h ( e )+E v v ( e ))+Σ e:k i ≠k j w ( e ) H p E p ,

wherein e corresponds to an edge in a core, w corresponds to a weight of edge e, E h corresponds to power consumed for a hop of a spike sent in a horizontal distance, h corresponds to a horizontal distance of edge e, E v corresponds to power consumed for a hop of a spike sent in a vertical distance, v corresponds to a vertical distance of edge e, H p corresponds to the inter-chip hop length, E p corresponds to power consumed when a spike travels across a chip boundary, and k i corresponds to a chip index;

locating at least one faulty router of the plurality of routers;

modeling a placement blockage, the placement blocking including at least a core of the plurality of cores associated with the faulty router;

determining a placement of a plurality of logical cores on the physical neurosynaptic cores by minimizing the weighted wire length, the placement minimizing power consumption of the spike communication while avoiding the faulty router; and

configuring the physical neurosynaptic cores to execute the plurality of logical cores according to the determined placement.

7. The method of claim 6 , wherein:

the placement of the neurosynaptic cores is substantially along rows and columns of a grid;

the placement blockage includes at least a column of the grid.

8. The method of claim 6 , wherein:

the placement of the neurosynaptic cores is substantially along a grid;

the placement blockage includes at least a row of the grid.

9. The method of claim 6 , wherein:

the placement of the neurosynaptic cores is substantially along a grid;

the placement blockage includes at least a row and a column of the grid.

10. The method of claim 6 , wherein the minimizing the weighted wire length comprises applying a VLSI placement algorithm.

11. The method of claim 10 , wherein the VLSI placement algorithm comprises partitioning-based placement.

12. The method of claim 6 , wherein the plurality of neurosynaptic cores is divided among a plurality of chips.

13. The method of claim 6 , further comprising:

locating at least one faulty core of the plurality of neurosynaptic cores; and

modeling a second placement blockage at the location of the at least one faulty core.

14. A computer program product for fault-tolerant power-driven synthesis, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

modeling power consumption of spike communication in a neurosynaptic network as weighted wire length, the neurosynaptic network comprising a plurality of physical neurosynaptic cores interconnected by a plurality of routers, the weighted wire length being weighted by spike frequency among the plurality of physical neurosynaptic cores, the weighted wire length being proportional to a sum of a number of intra-chip hops that each spike travels and an inter-chip hop length, wherein the weighted wire length, P, is determined by the equation:

P =Σ e ∈E w ( e )( E h h ( e )+ E v v ( e ))+Σ e:k i ≠k j w ( e ) H p E p ,

wherein e corresponds to an edge in a core, w corresponds to a weight of edge e, E h corresponds to power consumed for a hop of a spike sent in a horizontal distance, h corresponds to a horizontal distance of edge e, E v corresponds to power consumed for a hop of a spike sent in a vertical distance, v corresponds to a vertical distance of edge e, H p corresponds to the inter-chip hop length, E p corresponds to power consumed when a spike travels across a chip boundary, and k i corresponds to a chip index;

locating at least one faulty core of the plurality of physical neurosynaptic cores;

modeling a placement blockage at the location of the at least one faulty core; and

determining a placement of a plurality of logical cores on the physical neurosynaptic cores by minimizing the weighted wire length, the placement minimizing power consumption of the spike communication while avoiding the faulty core; and

configuring the physical neurosynaptic cores to execute the plurality of logical cores according to the determined placement.

15. The computer program product of claim 14 , wherein the minimizing the weighted wire length comprises applying a VLSI placement algorithm.

16. The computer program product of claim 15 , wherein the VLSI placement algorithm comprises partitioning-based placement.

17. The computer program product of claim 14 , further comprising:

locating at least one faulty router of the plurality of routers; and

modeling a second placement blockage, the second placement blockage including at least a core of the plurality of cores associated with the faulty router.

18. The computer program product of claim 14 , wherein the plurality of neurosynaptic cores is divided among a plurality of chips.

19. A computer program product for fault-tolerant power-driven synthesis, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

modeling power consumption of spike communication in a neurosynaptic network as weighted wire length, the neurosynaptic network comprising a plurality of physical neurosynaptic cores interconnected by a plurality of routers, the weighted wire length being weighted by spike frequency among the plurality of physical neurosynaptic cores, the weighted wire length being proportional to a sum of a number of intra-chip hops that each spike travels and an inter-chip hop length, wherein the weighted wire length, P, is determined by the equation:

P =Σ e ∈E w ( e )( E h h ( e )+ E v v ( e ))+Σ e:k i ≠k j w ( e ) H p E p ,

wherein e corresponds to an edge in a core, w corresponds to a weight of edge e, E h corresponds to power consumed for a hop of a spike sent in a horizontal distance, h corresponds to a horizontal distance of edge e, E v corresponds to power consumed for a hop of a spike sent in a vertical distance, v corresponds to a vertical distance of edge e, H p corresponds to the inter-chip hop length, E p corresponds to power consumed when a spike travels across a chip boundary, and k i corresponds to a chip index;

locating at least one faulty router of the plurality of routers;

modeling a placement blockage, the placement blocking including at least a core of the plurality of cores associated with the faulty router; and

determining a placement of a plurality of logical cores on the physical neurosynaptic cores by minimizing the weighted wire length, the placement minimizing power consumption of the spike communication while avoiding the faulty router; and

configuring the physical neurosynaptic cores to execute the plurality of logical cores according to the determined placement.

20. The computer program product of claim 19 , wherein:

the placement of the neurosynaptic cores is substantially along rows and columns of a grid; and

the placement blockage includes at least a column of the grid.