IP Library › Granted Patent US 10,553,431
Granted Patent B2
US 10,553,431 · App. 15/696,498 · Granted Feb 4, 2020

Cut last self-aligned litho-etch patterning

Inventors: Kuan-Wei Huang (Taoyuan, TW); Chia-Ying Lee (New Taipei, TW); Ming-Chung Liang (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L21/0338H01L21/0332H01L21/0335H01L21/0337H01L27/11
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Quick Facts
Patent No.
US 10,553,431
App. No.
15/696,498
Granted
Feb 4, 2020
Kind
B2
Abstract

The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.

Claims (42)

1. A method of performing a semiconductor fabrication process, comprising:

forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments;

forming a cut material over a part of the horizontally extending segment;

removing the horizontally extending segment of the spacer material not covered by the cut material; and

patterning a layer under the masking layer according to the masking layer and the spacer material.

2. The method of claim 1 , further comprising:

removing a first segment of the masking layer prior to forming the spacer material, wherein removing the first segment of the masking layer defines the sidewalls of the masking layer; and

removing a second segment of the masking layer, wherein the second segment of the masking layer is surrounded by the spacer material on opposing sides.

3. The method of claim 2 , wherein the first segment of the masking layer is removed according to a first photolithography process and the second segment of the masking layer is removed according to a second photolithography process different than the first photolithography process.

4. The method of claim 3 , wherein the second photolithography process occurs after the first photolithography process.

5. The method of claim 1 , further comprising:

etching the masking layer to define a first opening bound on three sides by the spacer material and on a fourth side by the masking layer, and to define a second opening bound on three sides by the spacer material and on a fourth side by the masking layer; and

wherein the first opening is separated from the second opening by the spacer material.

6. The method of claim 1 , wherein removing the horizontally extending segment of the spacer material not covered by the cut material exposes a first plurality of regions of the layer that are separated by the cut material.

7. The method of claim 1 , wherein the spacer material comprises an ‘H’ shape from a top-view prior to removing the horizontally extending segment of the spacer material.

8. The method of claim 1 , wherein the cut material is laterally confined between the sidewalls of the masking layer.

9. The method of claim 1 , wherein forming the cut material over the part of the horizontally extending segment, comprises:

depositing the cut material over the part of the horizontally extending segment; and

etching back the cut material to a leave a residue of the cut material over the part of the horizontally extending segment.

10. The method of claim 1 , wherein the horizontally extending segment extends in opposing directions past the cut material as viewed from a top-view.

11. A method of performing a semiconductor fabrication process, comprising:

forming a spacer material extending between sidewalls of a masking layer;

forming a cut material having a bottommost surface that is both over a part of the spacer material and directly between sidewalls of the spacer material;

etching the spacer material with the cut material over the spacer material, wherein etching the spacer material with the cut material over the spacer material removes the spacer material from over a top surface of the masking layer to expose the top surface of the masking layer; and

patterning a layer under the masking layer according to the masking layer and the spacer material.

12. The method of claim 11 , further comprising:

removing a first segment of the masking layer prior to forming the spacer material, wherein removing the first segment of the masking layer defines the sidewalls of the masking layer; and

removing a second segment of the masking layer, wherein the second segment of the masking layer contacts the spacer material prior to being removed.

13. The method of claim 12 , wherein the first segment of the masking layer is removed according to a first photolithography process and the second segment of the masking layer is removed according to a second photolithography process different than the first photolithography process.

14. The method of claim 11 , wherein the spacer material has vertically extending segments along sidewalls of the masking layer and a horizontally extending segment recessed below tops of the vertically extending segments and connecting the vertically extending segments.

15. The method of claim 11 , wherein patterning the layer under the masking layer results in openings within the layer that are separated by an end to end space that is less than a minimum space achievable using a single photomask.

16. The method of claim 11 , wherein the spacer material comprises silicon oxide, silicon nitride, titanium oxide, or aluminum oxide.

17. The method of claim 11 , wherein the cut material comprises silicon.

18. A method of semiconductor processing, comprising:

forming a masking structure having sidewalls defining a first plurality of openings separated from sidewalls defining a second plurality of openings along a first direction by a spacer material and a first masking layer, wherein the sidewalls defining the first plurality of openings are separated along a second direction by the spacer material and an overlying cut material; and

patterning a layer under the masking structure according to the masking structure.

19. The method of claim 18 , wherein forming the masking structure comprises:

etching a masking layer to form a plurality of openings;

depositing the spacer material over the masking layer and within the plurality of openings;

forming the cut material over the spacer material; and

etching the spacer material with the cut material over the spacer material.

20. The method of claim 18 , wherein the first plurality of openings are formed using a first photolithography process and the second plurality of openings are formed using a second photolithography process different than the first photolithography process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2017
From: HUANG, KUAN-WEI; LEE, CHIA-YING; LIANG, MING-CHUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 043500/0097 →
Continuity (3)
Continuation 15170090 · Jun 1, 2016
Continuation 14154454 · Jan 14, 2014
Related Publication 20170365472A1 · Dec 21, 2017