Substrate strip including conductive plane around periphery of chip mounting regions and method of manufacturing semiconductor package using the same
A substrate includes a substrate body including a plurality of chip mounting regions and a peripheral region surrounding the plurality of chip mounting regions, each of the chip mounting regions including a conductive plane. The substrate further includes a conductive support structure located in the peripheral region, first conductive lines connected between the conductive planes of adjacent chip mounting regions, and second conductive lines connected between the conductive support structure and the conductive planes of chip mounting regions located adjacent the peripheral region.
1. A semiconductor package comprising:
a substrate having an upper surface, a lower surface, and a plurality of side surfaces;
a plurality of conductive pads arranged on a central region of the upper surface of the substrate;
a conductive plane that is contiguous and extends around an entire periphery of the substrate adjacent the plurality of side surfaces of the substrate, when viewed from a plan view;
a plurality of conductive lines each having a proximate end connected to the conductive plane and a distal end flush with one of the plurality of side surfaces of the substrate;
a semiconductor chip mounted on the central region of the upper surface of the substrate and electrically connected to the plurality of conductive pads;
an encapsulate covering the upper surface of the substrate and the semiconductor chip;
terminal connections located on the lower surface of the substrate and electrically connected to the semiconductor chip,
wherein the plurality of conductive pads and the conductive plane are located on the upper surface of the substrate, and
wherein the conductive plane is spaced apart from the plurality of side surfaces of the substrate,
wherein the conductive plane is included in a stack of conductive planes,
the stack of conductive planes comprising the conductive plane and a plurality of additional conductive planes vertically spaced from each other,
wherein the plurality of additional conductive planes are aligned below the upper surface of the substrate, and
wherein each of the conductive lines is included in one of plural stacks of conductive lines respectively connected to and co-planer with the conductive plane and the additional conductive planes included in the stack of conductive planes; and
vias connecting the conductive plane and the additional conductive planes included in the stack of conductive planes to each other.
2. The semiconductor package of claim 1 , wherein the plurality of conductive lines are embedded within the substrate below the upper surface of the substrate.
3. The semiconductor package of claim 1 , wherein side surfaces of the encapsulate are flush with the plurality of side surfaces of the substrate, respectively.
4. The semiconductor package of claim 1 , wherein the proximate ends of the conductive lines are co-planar with the conductive plane and the plurality of additional conductive planes.
5. The semiconductor package of claim 4 , wherein the conductive lines are contiguous with the conductive plane and the plurality of additional conductive planes at the proximate ends of the conductive lines.