Compact OTP/MTP memory device including a cavity formed between a substrate and a buried oxide layer
Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
1. A device comprising:
a substrate having a buried oxide (BOX) layer formed over the substrate and a cavity formed between the substrate and the BOX layer and between a pair of isolation structures formed on the substrate;
first and second silicon-on-insulator (SOT) regions formed on the BOX layer end to end with a gap in between, the first and second SOI regions formed between the pair of isolation structures;
first and second replacement metal gates (RMGs), laterally separated, formed over and perpendicular to the first and second SOI regions, respectively;
at least one third RMG formed between the first and second RMGs on the BOX layer through the gap;
a source/drain (S/D) region formed in each of the first and second SOI regions adjacent to the first and second RMGs, respectively, remote from the at least one third RMG; and
a bit line (BL) connected to the S/D region or the at least one third RMG.
2. The device according to claim 1 , wherein each of the first and second RMGs is utilized as a word line (WL) and each third RMG is utilized as a source line (SL) or a SL is connected to the S/D region.
3. The device according to claim 1 , further comprising:
an L-shaped liner on each sidewall of each first, second, and third RMG;
a first spacer on each L-shaped liner of the first and second RMGs; and
a second spacer on each L-shaped liner of each third RMG.
4. The device according to claim 3 , wherein the second spacer being separated from the first spacers, the device further comprising second source/drain regions formed between the at least one third RMG and the adjacent first and second RMGs.
5. The device according to claim 3 , wherein the first and second spacers are formed with no gap in between.
6. The device according to claim 1 , further comprising at least one additional pair of first and second SOI regions parallel to and vertically spaced from the first and second SOI regions, the first and second RMGs extending over one or more of the additional first and second SOI regions, respectively.
7. The device according to claim 6 , wherein the at least one third RMG extends through each additional gap between the at least one additional pair of first and second SOI regions.
8. The device according to claim 1 , further comprising at least one additional pair of first and second SOI regions parallel to and vertically spaced from the first and second SOI regions, the first and second RMGs extending over the at least one additional pair of first and second SOI regions, respectively.
9. The device according to claim 8 , further comprising an additional at least one third RMG in each additional gap between each of the at least one additional pair of first and second SOI regions.
10. A device comprising:
a substrate having a buried oxide (BOX) layer formed over the substrate and a cavity formed between the substrate and the BOX layer;
first and second silicon-on-insulator (SOI) regions formed on the BOX layer with a gap in between;
first and second replacement metal gates (RMGs) formed over and perpendicular to the first and second SOI regions, respectively;
at least one third RMG formed between the first and second RMGs on the BOX layer through the gap;
a source/drain (S/D) region formed in each of the first and second SOI regions adjacent to the first and second RMGs, respectively; and
a bit line (BL) connected to the S/D region or the at least one third RMG.
11. The device according to claim 10 , wherein each of the first and second RMGs is utilized as a word line (WL) and each third RMG is utilized as a source line (SL) or a SL is connected to the S/D region.
12. The device according to claim 10 , further comprising:
an L-shaped liner on each sidewall of each first, second, and third RMG;
a first spacer on each L-shaped liner of the first and second RMGs; and
a second spacer on each L-shaped liner of each third RMG.
13. The device according to claim 12 , wherein the second spacer being separated from the first spacers, the device further comprising second source/drain regions formed between the at least one third RMG and the adjacent first and second RMGs.
14. The device according to claim 13 , wherein the first and second spacers are formed with no gap in between.