Bank-level fault management in a memory system
According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A second error is detected in the first bank number of a second memory device of the rank. Access requests for the first bank number of the second memory device are steered to the non-faulty bank having the second bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.
1. A method for bank-level fault management in a memory system having a plurality of ranks, each rank comprising a plurality of memory devices each having a plurality of banks, the method comprising:
detecting a first error in a first bank number of a first memory device of a rank;
marking the first bank number of the first memory device with a bank-level chip mark, the bank-level chip mark isolating declaration of an error condition to the first bank number;
detecting a second error in the first bank number of a second memory device of the rank;
steering access requests for the first bank number of the second memory device to the non-faulty bank having the second bank number; and
performing a bank-level fault management action based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.
2. The method of claim 1 , further comprising:
overwriting in-use data storage of the second bank number with data associated with the first bank number of the second memory device based on determining that a non-faulty bank is available at the second bank number.
3. The method of claim 1 , further comprising:
receiving an access request for the second bank number; and
using the error-correcting code decoder to generate recovery data associated with the non-faulty bank having the second bank number after being overwritten by data associated with the first bank number of the second memory device.
4. The method of claim 1 , wherein the non-faulty bank having the second bank number is located in the second memory device.
5. The method of claim 1 , wherein the non-faulty bank is located on a second rank.
6. The method of claim 5 , wherein the rank and the second rank are located on separate memory modules coupled to a memory buffer device that controls bank steering between the rank and the second rank.
7. The method of claim 1 , further comprising: based on detecting a subsequent error condition at the first bank number comprising the bank-level chip mark, marking the first bank number as a faulty bank; and supporting address range de-allocation for an address space of the faulty bank.
8. A memory system, comprising:
a plurality of ranks, each rank comprising a plurality of memory devices each having a plurality of banks; and
a memory buffer device coupled to at least one of the ranks, the memory system configured to:
detect a first error in a first bank number of a first memory device of a rank;
mark the first bank number of the first memory device with a bank-level chip mark, the bank-level chip mark isolating declaration of an error condition to the first bank number;
detect a second error in the first bank number of a second memory device of the rank;
steer access requests for the first bank number of the second memory device to the non-faulty bank having the second bank number; and
perform a bank-level fault management action based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.
9. The memory system of claim 8 , wherein the memory system is further configured to:
receive an access request for the second bank number; and
use the error-correcting code decoder to generate recovery data associated with the in-use data storage of the non-faulty bank having the second bank number after being overwritten by the data associated with the first bank number of the second memory device.
10. The memory system of claim 8 , wherein the non-faulty bank having the second bank number is located in the second memory device.
11. The memory system of claim 8 , wherein the non-faulty bank is located on a second rank.
12. The memory system of claim 11 , wherein the rank and the second rank are located on separate memory modules coupled to the memory buffer device that controls bank steering between the rank and the second rank.
13. The memory system of claim 8 , wherein the memory system is further configured to:
mark the first bank number as a faulty bank based on detecting a subsequent error condition at the first bank number comprising the bank-level chip mark; and
support address range de-allocation for an address space of the faulty bank.
14. A computer program product for bank-level fault management in a memory system having a plurality of ranks, each rank comprising a plurality of memory devices each having a plurality of banks, the computer program product comprising:
a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising:
detecting a first error in a first bank number of a first memory device of a rank;
marking the first bank number of the first memory device with a bank-level chip mark, the bank-level chip mark isolating declaration of an error condition to the first bank number;
detecting a second error in the first bank number of a second memory device of the rank;
steering access requests for the first bank number of the second memory device to the non-faulty bank having the second bank number; and
performing a bank-level fault management action based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.
15. The computer program product of claim 14 , wherein the program instructions are further configured to cause the processing circuit to perform the method comprising:
receiving an access request for the second bank number; and
using the error-correcting code decoder to generate recovery data associated with the non-faulty bank having the second bank number after being overwritten by data associated with the first bank number of the second memory device.
16. The computer program product of claim 14 , wherein the non-faulty bank having the second bank number is located in the second memory device.
17. The computer program product of claim 14 , wherein the non-faulty bank is located on a second rank.
18. The computer program product of claim 17 , wherein the rank and the second rank are located on separate memory modules coupled to a memory buffer device that controls bank steering between the rank and the second rank.
19. The computer program product of claim 14 , wherein the program instructions are further configured to cause the processing circuit to perform the method comprising:
based on detecting a subsequent error condition at the first bank number comprising the bank-level chip mark, marking the first bank number as a faulty bank; and
supporting address range de-allocation for an address space of the faulty bank.
20. The computer program product of claim 14 , wherein the program instructions are further configured to cause the processing circuit to perform the method comprising:
overwriting in-use data storage of the second bank number with data associated with the first bank number of the second memory device based on determining that a non-faulty bank is available at the second bank number.