Electronic assemblies having a cooling chip layer with impingement channels and through substrate vias

1. An electronics assembly comprising:

a cooling chip structure comprising:

a target layer comprising a plurality of fins defining a plurality of microchannels;

a jet impingement layer coupled to the plurality of fins of the target layer, the jet impingement layer comprising:

a plurality of jet channels disposed within the jet impingement layer; and

a plurality of through substrate vias disposed within the: impingement layer, wherein:

the plurality of through substrate vias is electrically conductive and is electrically coupled to the target layer;

a first jet channel of the plurality of jet channels is closer to a first through substrate via of the plurality of through substrate vias than a second jet channel of the plurality of jet channels; and

the first jet channel comprises a first cross-sectional fluid area that is smaller than a second cross-sectional fluid area of the second jet channel; and

a fluid inlet port and a fluid outlet port, wherein the fluid inlet port and the fluid outlet port are fluidly coupled to the plurality of jet channels of the jet impingement layer.

2. The electronics assembly of claim 1 , further comprising a semiconductor device stack comprising:

a semiconductor device comprising a first device surface opposite a second device surface and a semiconductor material disposed between the first device surface and the second device surface; and

a second electrode electrically and thermally coupled to the second device surface of the semiconductor device, wherein the first device surface is opposite the second device surface, and the plurality of through substrate vias is electrically coupled to the target layer, wherein the target layer defines a first electrode.

3. The electronics assembly of claim 2 , wherein the plurality of jet channels direct dielectric cooling fluid onto a plurality of hotspots formed where the plurality of through substrate vias electrically couple to the semiconductor device stack.

4. The electronics assembly of claim 1 , further comprising:

a third electrode electrically coupled to the plurality of through substrate vias opposite the target layer of the cooling chip structure; and

a gap between a surface of the jet impingement layer and the third electrode wherein a portion of the jet impingement layer surrounding each through substrate via of the plurality of through substrate vias has a first height that is greater than a second height of the jet impingement layer surrounding each jet channel of the plurality of jet channels.

5. The electronics assembly of claim 1 , wherein the plurality of microchannels disperses a dielectric cooling fluid flow introduced by the plurality of jet channels across the target layer.

6. The electronics assembly of claim 1 , wherein the plurality of through substrate vias is configured in a non-symmetrical arrangement within the cooling chip structure.

7. The electronics assembly of claim 1 , wherein the plurality of through substrate vias is configured in a symmetrical arrangement within the cooling chip structure.

8. The electronics assembly of claim 1 , wherein a third jet channel of the plurality of jet channels is positioned at a greater distance from the first through substrate via than the second jet channel, and the third jet channel has a third cross-sectional fluid area greater than the second cross-sectional fluid area of the second jet channel.

9. The electronics assembly of claim 1 , wherein a third jet channel of the plurality of jet channels is positioned at a greater distance from the first through substrate via than the second jet channel, and the third jet channel has a third cross-sectional fluid area equal to the second cross-sectional fluid area of the second jet channel.