Nanosheet FET with box isolation on substrate
A method of fabricating a nanosheet semiconductor device includes depositing sacrificial material on a layer of silicon germanium (SiGe) above a substrate. A thickness of the sacrificial material is more than a thickness of the layer of SiGe. The method also includes forming nanosheet fins comprising alternating silicon (Si) nanosheets and silicon germanium (SiGe) layers on the sacrificial material, undercutting the SiGe layers to form divots, and forming a dummy gate structure above each of the nanosheet fins. A first liner is deposited to fill the divots and cover the nanosheet fins and the dummy gate structure. The sacrificial material and the first liner material are removed. The method also includes encapsulating the nanosheet fins and the dummy gate structure with a conformal liner, and performing an oxide fill to create a buried oxide (BOX) isolation between subsequently formed source and drain regions between the nanosheet fins and the substrate.
1. A method of fabricating a nanosheet semiconductor device, the method comprising:
depositing sacrificial material on a layer of silicon germanium (SiGe) above a substrate, wherein a thickness of the sacrificial material is more than a thickness of the layer of SiGe;
forming nanosheet fins comprising alternating silicon (Si) nanosheets and silicon germanium (SiGe) layers on the sacrificial material;
undercutting the SiGe layers to form divots at a first end and a second end of each of the nanosheet fins;
forming a dummy gate structure above each of the nanosheet fins;
depositing a first liner to fill the divots and conformally cover the nanosheet fins and the dummy gate structure;
removing the sacrificial material and removing the first liner material after removal of the sacrificial material;
encapsulating the nanosheet fins and the dummy gate structure with a conformal liner; and
performing an oxide fill to create a buried oxide (BOX) isolation between subsequently formed source and drain regions between the nanosheet fins and the substrate.
2. The method according to claim 1 , wherein the depositing the sacrificial material includes controlling the thickness of the sacrificial material to be on the order of ten times the thickness of the layer of SiGe.
3. The method according to claim 1 further comprising depositing the conformal liner to surround the oxide fill below the nanosheet fins.
4. The method according to claim 1 , wherein the forming the dummy gate structure includes depositing and etching spacers to define a region of the dummy gate structure.
5. The method according to claim 1 further comprising forming a recess in the oxide fill between the nanosheet fins.
6. The method according to claim 5 further comprising performing an epitaxy to grow the source region on one side of each of the nanosheet fins and the drain region on an opposite side of each of the nanosheet fins, in and above the recess.
7. The method according to claim 1 further comprising replacing the dummy gate structure with a gate structure above each of the nanosheet fins.
8. The method according to claim 7 further comprising removing the SiGe layers of the nanosheet fins.
9. The method according to claim 8 further comprising depositing a gate metal as part of the gate structure and to fill gaps resulting from removal of the SiGe layers to create a gate-all-around configuration.
10. The method according to claim 1 further comprising forming contacts above the source and drain regions.
11. A nanosheet semiconductor device, comprising:
an oxide above a silicon germanium (SiGe) layer formed on a substrate, wherein a thickness of a thinnest portion of the oxide is more than a thickness of the SiGe layer;
silicon (Si) nanosheets formed above a thickest portion of the oxide, wherein a gap between adjacent ones of the Si nanosheets is filled on a first end and a second end with a liner material;
a source region adjacent the first end of the Si nanosheets and a drain region adjacent the second end of the Si nanosheets, wherein the source region and the drain region are formed on the thinnest portion of the oxide; and
a second liner material between the SiGe layer and the oxide.
12. The device according to claim 11 , wherein a thickness of the thinnest portion of the oxide is on an order of ten times the thickness of the SiGe layer.
13. The device according to claim 11 , wherein the oxide below the Si nanosheets is surrounded by the second liner material.
14. The device according to claim 11 further comprising a gate formed above the Si nanosheets.
15. The device according to claim 14 , wherein the gate includes a gate metal and a fill metal.
16. The device according to claim 15 , wherein the gap between the adjacent ones of the Si nanosheets is filled with the gate metal between the liner material on the first end and the second end.
17. The device according to claim 14 , wherein the gate is formed between spacers.
18. The device according to claim 11 , wherein the oxide is silicon dioxide.
19. The device according to claim 11 further comprising contacts formed above the source region and the drain region.