Semiconductor device structure and methods of forming the same
A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.
1 . A semiconductor device structure, comprising:
a plurality of semiconductor layers;
a first source/drain epitaxial feature in contact with the plurality of semiconductor layers, wherein the first source/drain epitaxial feature comprises a top portion and a bottom portion;
a spacer comprising a gate spacer portion and one or more source/drain spacer portions, wherein each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with the bottom portion of the first source/drain epitaxial feature, wherein a slant surface of the top portion of the first source/drain epitaxial feature is disposed over a top surface of the source/drain spacer portion of the one or more source/drain spacer portions, and a gap is formed between the slant surface of the top portion of the first source/drain epitaxial feature and the top surface of the source/drain spacer portion of the one or more source/drain spacer portions;
a dielectric feature disposed adjacent the top portion of the first source/drain epitaxial feature and the source/drain spacer portion of the one or more source/drain spacer portions, wherein the dielectric feature has a second height substantially greater than the first height; and
an interlayer dielectric (ILD) layer disposed over the dielectric feature.
2 . The semiconductor device structure of claim 1 , further comprising a gate electrode layer surrounding at least a portion of each of the plurality of semiconductor layers.
3 . The semiconductor device structure of claim 2 , further comprising an inner spacer disposed between the gate electrode layer and the first source/drain epitaxial feature.
4 . The semiconductor device structure of claim 3 , wherein the inner spacer comprises a first dielectric material, and the spacer comprises a second dielectric material different from the first dielectric material.
5 . The semiconductor device structure of claim 1 , further comprising a second source/drain epitaxial feature, wherein the dielectric feature is disposed between the first and second source/drain epitaxial features.
6 . The semiconductor device structure of claim 5 , wherein the bottom portion of the first source/drain epitaxial feature has substantially straight sidewalls, and the second source/drain epitaxial feature comprises a bottom portion having substantially straight sidewalls.
7 . The semiconductor device structure of claim 6 , wherein the one or more source/drain spacer portions comprise first and second pairs of source/drain spacer portions, the first pair of source/drain spacer portions is in contact with the substantially straight sidewalls of the bottom portion of the first source/drain epitaxial feature, and the second pair of source/drain spacer portions is in contact with the substantially straight sidewalls of the bottom portion of the second source/drain epitaxial features.
8 . The semiconductor device structure of claim 7 , wherein one source/drain spacer portion of the first pair of source/drain spacer portions and one source/drain spacer portion of the second pair of source/drain spacer portions are in contact with the dielectric feature.
9 . A semiconductor device structure, comprising:
a plurality of semiconductor layers;
a source/drain epitaxial feature interfacing the plurality of semiconductor layers;
a gate electrode layer surrounding at least a portion of each of the plurality of semiconductor layers;
a gate dielectric layer, wherein the gate electrode layer is disposed on the gate dielectric layer, wherein a distance is between a bottom of the gate dielectric layer and a top of a topmost semiconductor layer of the plurality of semiconductor layers;
a spacer comprising a gate spacer portion and one or more source/drain spacer portions, wherein each source/drain spacer portion has a first height, and the first height is about 20 percent to about 75 percent of the distance, wherein a slant surface of the source/drain epitaxial feature is disposed over a top surface of a source/drain spacer portion of the one or more source/drain spacer portions, and a gap is formed between the slant surface of the source/drain epitaxial feature and the top surface of the source/drain spacer portion of the one or more source/drain spacer portions;
a dielectric feature disposed adjacent a top portion of the source/drain epitaxial feature; and
an interlayer dielectric (ILD) layer disposed over the dielectric feature.
10 . The semiconductor device structure of claim 9 , wherein the dielectric feature is interfacing the top portion of the source/drain epitaxial feature.
11 . The semiconductor device structure of claim 9 , wherein the one or more source/drain spacer portions comprises two source/drain spacer portions.
12 . The semiconductor device structure of claim 11 , wherein a bottom portion of the source/drain epitaxial feature is clamped by the two source/drain spacer portions.
13 . The semiconductor device structure of claim 12 , wherein the dielectric feature is in contact with one of the two source/drain spacer portions.
14 . The semiconductor device structure of claim 13 , wherein the dielectric feature comprises:
a liner;
a dielectric material disposed on the liner; and
a high-K dielectric layer disposed on the liner and the dielectric material.
15 . The semiconductor device structure of claim 9 , wherein the one or more source/drain spacer portions are substantially perpendicular to the gate spacer portion.
16 . A semiconductor device structure, comprising:
a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a top portion and a bottom portion;
a spacer comprising a gate spacer portion and two source/drain spacer portions, wherein the two source/drain spacer portions are in contact with opposite sides of the bottom portion, each source/drain spacer portion is substantially perpendicular to the gate spacer portion, and each source/drain spacer portion has a height substantially less than a height of the gate spacer portion, wherein a slant surface of the top portion of the source/drain epitaxial feature is disposed over a top surface of a source/drain spacer portion of the two source/drain spacer portions, and a gap is formed between the slant surface of the top portion of the source/drain epitaxial feature and the top surface of the source/drain spacer portion of the two source/drain spacer portions;
a dielectric feature disposed adjacent the top portion of the source/drain epitaxial feature; and
an interlayer dielectric (ILD) layer disposed over the dielectric feature.
17 . The semiconductor device structure of claim 16 , wherein the dielectric feature is in contact with one of the two source/drain spacer portions.
18 . The semiconductor device structure of claim 17 , wherein the dielectric feature has a height substantially greater than the height of the source/drain spacer portion.
19 . The semiconductor device structure of claim 18 , wherein the height of the dielectric feature is substantially less than the height of the gate spacer portion.
20 . The semiconductor device structure of claim 16 , wherein the top portion of the source/drain epitaxial feature is in contact with the gate spacer portion.