Half buried nFET/pFET epitaxy source/drain strap
A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.
1. A method for reducing parasitic capacitance, the method comprising:
forming a p-type epitaxial region and an n-type epitaxial region over a substrate;
depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region;
depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween;
selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions;
depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions;
selectively etching the first and second dielectrics to form a strapped contact; and
applying a metallization layer over the strapped contact.
2. The method of claim 1 , wherein the strapped contact has a substantially “T-shaped” configuration.
3. The method of claim 1 , wherein the strapped contact includes portions of the first dielectric.
4. The method of claim 3 ,
wherein the portions of the second dielectric prevent direct contact between the p-type and n-type epitaxial regions, and the first dielectric.
5. The method of claim 1 , wherein the strapped contact extends above a top surface of the p-type and n-type epitaxial regions.
6. The method of claim 1 , wherein the strapped contact connects the p-type epitaxial region to the n-type epitaxial region.
7. The method of claim 1 , wherein the metallization layer directly contacts the top surfaces of the p-type and n-type epitaxial regions.
8. The method of claim 1 , wherein the airgap is formed below the top surfaces of the p-type and n-type epitaxial regions.
9. A method for reducing parasitic capacitance, the method comprising:
forming nanosheet stacks including alternating layers of a first semiconductor material and a second semiconductor material over a substrate ( 10 );
depositing a dummy gate over the nanosheet stacks;
forming a p-type epitaxial region and an n-type epitaxial region adjacent each of the nanosheet stacks;
depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region;
depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween;
selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions;
depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions;
removing the dummy gate and the first semiconductor material of the nanosheet stacks resulting in openings;
depositing a high-k metal gate within the openings;
selectively etching the first and second dielectrics to form a strapped contact; and
applying a metallization layer over the strapped contact.
10. The method of claim 9 , wherein the strapped contact has a substantially “T-shaped” configuration.
11. The method of claim 9 , wherein the strapped contact includes portions of the first dielectric.
12. The method of claim 11 ,
wherein the portions of the second dielectric prevent direct contact between the p-type and n-type epitaxial regions, and the first dielectric.
13. The method of claim 9 , wherein the strapped contact extends above a top surface of the p-type and n-type epitaxial regions.
14. The method of claim 9 , wherein the strapped contact connects the p-type epitaxial region to the n-type epitaxial region.
15. The method of claim 9 , wherein the metallization layer directly contacts the top surfaces of the p-type and n-type epitaxial regions.
16. The method of claim 9 , wherein the airgap is formed below the top surfaces of the p-type and n-type epitaxial regions.