Semiconductor memory device
A semiconductor memory device, including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a channel semiconductor layer extending in the first direction and including a first portion facing the plurality of the first conductive layers and a second portion further from the substrate than the first portion; a memory layer arranged between the first portion of the channel semiconductor layer and the plurality of the first conductive layers and including a memory part capable of storing data; and a first semiconductor layer connected to the second portion of the channel semiconductor layer, the first semiconductor layer including crystalline semiconductor containing a first impurity, and the channel semiconductor layer including a crystal grain having a crystal grain size larger than a thickness thereof.
1. A semiconductor memory device, comprising:
a substrate;
a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate;
a channel semiconductor layer extending in the first direction and including a first portion facing the plurality of the first conductive layers, a second portion further from the substrate than the first portion, and, a third portion nearer to the substrate than the first portion, the channel semiconductor layer including a crystal grain having a crystal grain size larger than a thickness in a second direction of the channel semiconductor layer, the second direction intersecting the first direction;
a memory layer arranged between the first portion of the channel semiconductor layer and the plurality of the first conductive layers and including a memory part capable of storing data;
a first semiconductor layer directly contacting with the second portion of the channel semiconductor layer, the first semiconductor layer including crystalline semiconductor containing phosphorous; and
a second semiconductor layer directly contacting with the third portion of the channel semiconductor layer, the second semiconductor layer including phosphorous.
2. The semiconductor memory device according to claim 1 , wherein
the second semiconductor layer is a part of the substrate,
the substrate is directly contacting with the third portion of the channel semiconductor layer, and
a connecting region of the substrate connected to the channel semiconductor layer contains phosphorous.
3. A semiconductor memory device, comprising:
a substrate;
a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate;
a channel semiconductor layer extending in the first direction and including a first portion facing the plurality of the first conductive layers and a second portion nearer to the substrate than the first portion, the channel semiconductor layer including a crystal grain having a crystal grain size larger than a thickness in a second direction of the channel semiconductor layer, the second direction intersecting the first direction;
a memory layer arranged between the first portion of the channel semiconductor layer and the plurality of the first conductive layers and including a memory part capable of storing data; and
a first semiconductor layer directly contacting with the second portion of the channel semiconductor layer, the first semiconductor layer including phosphorous in a portion connected to the channel semiconductor layer.
4. The semiconductor memory device according to claim 3 , wherein
the first semiconductor layer is a part of the substrate,
the substrate is directly contacting with the second portion of the channel semiconductor layer, and
a connecting region of the substrate connected to the channel semiconductor layer contains phosphorous.
5. The semiconductor memory device according to claim 3 , wherein
the first semiconductor layer includes a portion nearer to the first portion of the channel semiconductor layer than one end in the first direction of the channel semiconductor layer.
6. The semiconductor memory device according to claim 1 , wherein
the second semiconductor layer includes a portion nearer to the first portion of the channel semiconductor layer than one end in the first direction of the channel semiconductor layer.