Semiconductor devices and data storage systems including the same
A semiconductor device may include a lower interconnection structure electrically connected to circuit devices on a first substrate, a lower bonding structure connected to the lower interconnection structure and an upper bonding structure, an upper interconnection structure connected to the upper bonding structure, a second substrate on the upper interconnection structure, gate electrodes between the upper interconnection structure and the second substrate, channel structures penetrating through the gate electrodes. The gate electrodes may be spaced apart from each other in a vertical direction. The gate electrodes may include first and second gate electrodes. Each of the channel structures may include a channel layer, which may include a first semiconductor material layer adjacent to the first gate electrodes and a second semiconductor material layer adjacent to the second gate electrodes. Each of the first and second semiconductor material layers may have a single crystal structure or a single crystal-like structure.
1 . A semiconductor device comprising:
a first semiconductor structure including a first substrate, a plurality of circuit devices on the first substrate, a lower interconnection structure electrically connected to the plurality of circuit devices, and a lower bonding structure connected to the lower interconnection structure; and
a second semiconductor structure including a second substrate on the first semiconductor structure, a stack structure below the second substrate and including a plurality of gate electrodes and a plurality interlayer insulating layers alternately stacked in a vertical direction, and a plurality of channel structures penetrating through the stack structure and extending in the vertical direction, an upper interconnection structure below the stack structure, and an upper bonding structure connected to the upper interconnection structure and bonded to the lower bonding structure, wherein
the vertical direction is perpendicular to the second substrate,
each of the plurality of channel structures includes a channel layer,
the stack structure includes a first stack structure and a second stack structure below the first stack structure,
the plurality of channel structures each includes a first channel structure and a second channel structure,
the first channel structure penetrates through the first stack structure,
the second channel structure penetrates through the second stack structure, and
the plurality of channel structures each further include a metal-semiconductor compound layer in a region of the channel layer adjacent to a boundary between the first channel structure and the second channel structure.
2 . The semiconductor device of claim 1 , wherein
the channel layer includes a first semiconductor material layer above the metal-semiconductor compound layer and a second semiconductor material layer below the metal-semiconductor compound layer, and
the first semiconductor material layer and the second semiconductor material layer each have a single crystal structure or a single crystal-like structure.
3 . The semiconductor device of claim 2 , wherein
the first semiconductor material layer is in contact with an upper surface of the metal-semiconductor compound layer,
the second semiconductor material layer is in contact with a lower surface of the metal-semiconductor compound layer, and
the metal-semiconductor compound layer, the first semiconductor material layer, and the second semiconductor material layer are electrically connected to each other.
4 . The semiconductor device of claim 2 , wherein
an external side surface of the first semiconductor material layer and an external side surface of the second semiconductor material layer are coplanar with an external side surface of the metal-semiconductor compound layer, and
each of the plurality of channel structures further includes a gate dielectric layer surrounding the external side surface of the first semiconductor material layer, the external side surface of the second semiconductor material layer, and the external side surface of the metal-semiconductor compound layer.
5 . The semiconductor device of claim 4 , wherein
at least one of the plurality of channel structures penetrates through the stack structure and extends into the second substrate,
in at least one of the plurality of channel structures, an upper end portion of the channel layer is in direct contact with the second substrate, and
in at least one of the plurality of channel structures, a lower end portion of the channel layer is surrounded by the gate dielectric layer.
6 . The semiconductor device of claim 1 , wherein
the metal-semiconductor compound layer is on a level between a lowermost gate electrode of the first stack structure and an uppermost gate electrode of the second stack structure, and
the lowermost gate electrode of the first stack structure and the uppermost gate electrode of the second stack structure are among the plurality of gate electrodes in the second semiconductor structure.
7 . The semiconductor device of claim 1 , wherein
the metal-semiconductor compound layer has a length of about 10 nm or less in the vertical direction.
8 . The semiconductor device of claim 1 , wherein
the metal-semiconductor compound layer includes at least one of nickel (Ni), cobalt (Co), platinum (Pt), and palladium (Pd).
9 . The semiconductor device of claim 1 , wherein
the channel layer includes a first semiconductor material layer above the metal-semiconductor compound layer and a second semiconductor material layer below the metal-semiconductor compound layer,
the metal-semiconductor compound layer includes a first metal-semiconductor compound layer contacting the first semiconductor material layer and a second metal-semiconductor compound layer contacting the second semiconductor material layer.
10 . The semiconductor device of claim 9 , wherein
the first metal-semiconductor compound layer and the second metal-semiconductor compound layer are in contact with each other.
11 . The semiconductor device of claim 9 , wherein
the first metal-semiconductor compound layer and the second metal-semiconductor compound layer are spaced apart from each other, and
the channel layer further includes a third semiconductor material layer between the first metal-semiconductor compound layer and the second metal-semiconductor compound layer.
12 . The semiconductor device of claim 11 , wherein
a grain size of the third semiconductor material layer is smaller than a grain size of the first semiconductor material layer and a grain size of the second semiconductor material layer.
13 . The semiconductor device of claim 12 , wherein
the grain size of the first semiconductor material layer and the grain size of the second semiconductor material layer are within about 5 μm or more, and
the grain size of the third semiconductor material layer is about 0.4 μm or less.
14 . A semiconductor device comprising:
a first substrate;
a plurality of circuit devices on the first substrate;
a lower interconnection structure electrically connected to the plurality of circuit devices;
a lower bonding structure connected to the lower interconnection structure;
an upper bonding structure bonded to the lower bonding structure;
an upper interconnection structure connected to the upper bonding structure;
a second substrate on the upper interconnection structure;
a plurality of gate electrodes between the upper interconnection structure and the second substrate, the plurality of gate electrodes being spaced apart from each other and stacked in a vertical direction, and the plurality of gate electrodes including a plurality of first gate electrodes and a plurality of second gate electrodes below the plurality of first gate electrodes; and
a plurality of channel structures penetrating through the plurality of gate electrodes, each of the plurality of channel structures including a channel layer, wherein
the channel layer includes a first semiconductor material layer adjacent to the plurality of first gate electrodes and a second semiconductor material layer adjacent to the plurality of second gate electrodes, and
each of the first semiconductor material layer and the second semiconductor material layer has a single crystal structure or a single crystal-like structure.
15 . The semiconductor device of claim 14 , wherein
the channel layer includes a third semiconductor material layer between the first semiconductor material layer and the second semiconductor material layer,
the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer are electrically connected to each other, and
the third semiconductor material layer has a polycrystalline structure or an amorphous structure.
16 . The semiconductor device of claim 15 , wherein
the third semiconductor material layer is on a level between a lowermost gate electrode among the plurality of first gate electrodes and an uppermost gate electrode among the plurality of second gate electrodes.
17 . The semiconductor device of claim 15 , wherein
at least one of the plurality of channel structures further includes a first metal-semiconductor compound layer between the third semiconductor material layer and the first semiconductor material layer and a second metal-semiconductor compound layer between the third semiconductor material layer and the second semiconductor material layer.
18 . The semiconductor device of claim 17 , wherein
the first metal-semiconductor compound layer and the second metal-semiconductor compound layer include different metal elements.
19 . A data storage system comprising:
a semiconductor storage device including a first substrate, a plurality of circuit devices on the first substrate, a lower interconnection structure electrically connected to the plurality of circuit devices, a lower bonding structure connected to the lower interconnection structure, an upper bonding structure bonded to the lower bonding structure, an upper interconnection structure connected to the upper bonding structure, a second substrate on the upper interconnection structure, a plurality of gate electrodes between the upper interconnection structure and the second substrate, a plurality of channel structures penetrating through the plurality of gate electrodes, and input/output pads electrically connected to the plurality of circuit devices; and
a controller electrically connected to the semiconductor storage device through the input/output pads, wherein
the controller is configured to control the semiconductor storage device,
the plurality of gate electrodes are spaced apart from each other and stacked in a vertical direction,
the plurality of gate electrodes include a plurality of first gate electrodes and a plurality of second gate electrodes below the plurality of first gate electrodes,
each of the channel structures includes a channel layer,
the channel layer includes a first semiconductor material layer adjacent to the plurality of first gate electrodes and a second semiconductor material layer adjacent to the plurality of second gate electrodes, and
each of the first semiconductor material layer and the second semiconductor material layer has a single crystal structure or a single crystal-like structure.
20 . The data storage system of claim 19 , wherein
each of the plurality of channel structures further includes a metal-semiconductor compound layer between the first semiconductor material layer and the second semiconductor material layer, and
the first semiconductor material layer, the second semiconductor material layer, and the metal-semiconductor compound layer are electrically connected to each other.