FinFET semiconductor device with a dummy gate, first gate spacer and second gate spacer
A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
1. A semiconductor device comprising:
a substrate;
a plurality of active fins disposed on the substrate and including a first fin and a second fin;
an isolation layer disposed on the substrate and disposed between the first fin and the second fin;
a gate structure disposed on the plurality of active fins and the isolation layer, and including a gate insulation pattern and a gate electrode disposed on the gate insulation pattern, the gate insulation pattern covering a bottom surface and a sidewall of the gate electrode;
a first gate spacer disposed on a sidewall of gate structure; and
a second gate spacer disposed on a sidewall of the first gate spacer,
wherein a width of a lower portion of the gate structure is greater than a width of an upper portion of the gate structure, and
a thickness of a first portion of the first gate spacer is greater than a thickness of a second portion of the first gate spacer.
2. The semiconductor device of claim 1 , wherein a bottom surface of the first gate spacer is disposed higher than a bottom surface of the gate structure.
3. The semiconductor device of claim 1 , wherein a height of the first gate spacer is different from a height of the second gate spacer.
4. The semiconductor device of claim 1 , wherein the gate electrode includes a first portion where the sidewall of the gate electrode and the bottom surface of the gate electrode meet, and the first portion of the gate electrode is rounded.
5. The semiconductor device of claim 1 , wherein the second portion of the first gate spacer is disposed on the first portion of the first gate spacer.
6. The semiconductor device of claim 1 , further comprising:
a source/drain disposed on the first fin;
a metal silicide pattern disposed on the source/drain; and
a contact plug disposed on the metal silicide pattern.
7. The semiconductor device of claim 1 , wherein an upper portion of the second gate spacer does not contact the gate structure.
8. A semiconductor device comprising:
a substrate;
a plurality of active fins disposed on the substrate and including a first fin and a second fin;
an isolation layer disposed on the substrate and disposed between the first fin and the second fin;
a gate structure disposed on the plurality of active fins and the isolation layer, and
including a gate insulation pattern and a gate electrode disposed on the gate insulation pattern, the gate insulation pattern covering a bottom surface and a sidewall of the gate electrode;
a first gate spacer disposed on a sidewall of gate structure; and
a second gate spacer disposed on a sidewall of the first gate spacer,
wherein a width of a lower portion of the gate structure is greater than a width of an upper portion of the gate structure, and
a bottom surface of the first gate spacer is disposed higher than a bottom surface of the gate structure.
9. The semiconductor device of claim 8 , wherein a thickness of a first portion of the first gate spacer is greater than a thickness of a second portion of the first gate spacer, and
the second portion of the first gate spacer is disposed on the first portion of the first gate spacer.
10. The semiconductor device of claim 8 , wherein a height of the first gate spacer is different from a height of the second gate spacer.
11. The semiconductor device of claim 8 , wherein the gate electrode includes a first portion where the sidewall of the gate electrode and the bottom surface of the gate electrode meet, and
the first portion of the gate electrode is rounded.
12. The semiconductor device of claim 8 , wherein a lower portion of the gate insulation pattern includes a protruding portion.
13. The semiconductor device of claim 12 , wherein at least a portion of the first gate spacer is disposed on the protruding portion of the gate insulation pattern.
14. The semiconductor device of claim 8 , wherein each of the first gate spacer and the second gate spacer includes nitride.
15. The semiconductor device of claim 8 , further comprising:
a source/drain disposed on the first fin;
a metal silicide pattern disposed on the source/drain; and
a contact plug disposed on the metal silicide pattern.
16. A semiconductor device comprising:
a substrate;
a plurality of active fins disposed on the substrate and including a first fin and a second fin;
an isolation layer disposed on the substrate and disposed between the first fin and the second fin;
a gate structure disposed on the plurality of active fins and the isolation layer, and
including a gate insulation pattern and a gate electrode disposed on the gate insulation pattern, the gate insulation pattern covering a bottom surface and a sidewall of the gate electrode; and
a first gate spacer disposed on a sidewall of gate structure,
wherein a width of a lower portion of the gate structure is greater than a width of an upper portion of the gate structure,
a bottom surface of the first gate spacer is disposed higher than a bottom surface of the gate structure,
the gate electrode includes a first portion where the sidewall of the gate electrode and the bottom surface of the gate electrode meet,
the first portion of the gate electrode is rounded,
a thickness of a first portion of the first gate spacer is greater than a thickness of a second portion of the first gate spacer, and
the second portion of the first gate spacer is disposed on the first portion of the first gate spacer.
17. The semiconductor device of claim 16 , wherein further comprising a second gate spacer disposed on a sidewall of the first gate spacer,
wherein a height of the first gate spacer is different from a height of the second gate spacer.
18. The semiconductor device of claim 16 , wherein a lower portion of the gate insulation pattern includes a protruding portion, and
at least a portion of the first gate spacer is disposed on the protruding portion of the gate insulation pattern.
19. The semiconductor device of claim 18 , wherein the whole portion of the first gate spacer is disposed on the protruding portion of the gate insulation pattern.
20. The semiconductor device of claim 16 , further comprising:
a source/drain disposed on the first fin;
a metal silicide pattern disposed on the source/drain; and
a contact plug disposed on the metal silicide pattern.