Semiconductor device having gate isolation layer
A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.
1. A semiconductor device, comprising:
a substrate having a first region and a second region;
first active fins that extend in a first direction in the first region;
second active fins that extend in the first direction in the second region;
a first field insulating layer between the first active fins and extending in a second direction;
a second field insulating layer between the second active fins and extending in the second direction;
a gate line that extends in the second direction on the second field insulating layer; and
a gate isolation layer in contact with a side surface of the first field insulating layer in the second direction,
wherein an upper surface of the first field insulating layer is at a first level and an upper surface of the second field insulating layer is at a second level that is lower than the first level, and
wherein a bottom surface of the first field insulating layer is at a third level and a bottom surface of the second field insulating layer is at a fourth level that is different from the third level.
2. The semiconductor device as claimed in claim 1 , wherein:
the gate line includes a gate electrode, a gate insulating layer on a lower surface of the gate electrode, and a gate capping layer on an upper surface of the gate electrode, and
an upper surface of the first field insulating layer is at substantially a same level as an upper surface of the gate capping layer.
3. The semiconductor device as claimed in claim 2 , wherein a side surface of the gate isolation layer in the second direction is in contact with a portion of the gate insulating layer.
4. The semiconductor device as claimed in claim 2 , wherein an upper surface of the gate isolation layer is at substantially a same level as the upper surface of the gate capping layer.
5. The semiconductor device as claimed in claim 1 ,
wherein the gate line is on a straight line with the first field insulating layer along the second direction, and
wherein the gate isolation layer is between the first field insulating layer and the gate line.
6. The semiconductor device as claimed in claim 5 , further comprising gate spacers that extend in the second direction, the gate spacers being in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.
7. The semiconductor device as claimed in claim 6 , wherein the gate spacers include outer gate spacers in contact with each outer sidewalls of the first field insulating layer, the gate isolation layer, and the gate line.
8. The semiconductor device as claimed in claim 6 , wherein the gate spacers include inner gate spacers in contact with each inner sidewalls of the first field insulating layer, the gate isolation layer, and the gate line.
9. The semiconductor device as claimed in claim 1 , wherein a width of the first field insulating layer in the first direction is smaller than a width of the second field insulating layer in the first direction.
10. The semiconductor device as claimed in claim 1 , wherein the gate line has an asymmetric shape in the first direction.
11. The semiconductor device as claimed in claim 10 , wherein a portion of a lower surface of the gate line is in contact with the upper surface of the second field insulating layer.
12. A semiconductor device, comprising:
a substrate having a first region and a second region;
first active fins that extend in a first direction in the first region;
second active fins that extend in the first direction in the second region;
a first field insulating layer between the first active fins and extending in a second direction;
a second field insulating layer between the second active fins and extending in the second direction; and
a gate line that extends in the second direction on the second field insulating layer,
wherein a first level of an upper surface of the first field insulating layer is different from a second level of an upper surface of the second field insulating layer, and
wherein a first width of the first field insulating layer in the first direction is smaller than a second width of the second field insulating layer in the first direction.
13. The semiconductor device as claimed in claim 12 , wherein the second level is lower than the first level.
14. The semiconductor device as claimed in claim 12 , wherein a third level of a bottom surface of the first field insulating layer is different from a fourth level of a bottom surface of the second field insulating layer.
15. A semiconductor device, comprising:
a substrate having a first region and a second region;
first active fins that extend in a first direction in the first region;
second active fins that extend in the first direction in the second region;
a first field insulating layer between the first active fins and extending in a second direction;
a second field insulating layer between the second active fins and extending in the second direction;
a gate line that extends in the second direction and including a gate electrode, a gate insulating layer on a lower surface of gate electrode, and a gate capping layer on an upper surface of the gate electrode; and
a gate isolation layer between the first field insulating layer and the gate line,
wherein an upper surface of the first field insulating layer is at substantially a same level as an upper surface of the gate capping layer.
16. The semiconductor device as claimed in claim 15 , wherein the upper surface of the first field insulating layer, an upper surface of the gate isolation layer, and the upper surface of the gate capping layer are coplanar.
17. The semiconductor device as claimed in claim 15 ,
wherein a first side surface of the gate isolation layer in the second direction is in contact with a portion of the gate line, and
wherein a second side surface of the gate isolation layer in the second direction is in contact with the first field insulating layer.
18. The semiconductor device as claimed in claim 17 , wherein the first side surface of the gate isolation layer is in contact with a portion of the gate insulating layer.
19. The semiconductor device as claimed in claim 15 , wherein an upper surface of the first field insulating layer is at a first level and an upper surface of the second field insulating layer is at a second level that is lower than the first level.
20. The semiconductor device as claimed in claim 15 , wherein a bottom surface of the first field insulating layer is at a third level and a bottom surface of the second field insulating layer is at a fourth level that is different from the third level.