Semiconductor device having gate isolation layer

1. A semiconductor device, comprising:

a substrate having a first region and a second region;

first active fins that extend in a first direction in the first region;

second active fins that extend in the first direction in the second region;

a first field insulating layer between the first active fins and that extends in a second direction;

a second field insulating layer between the second active fins and extends in the second direction;

a gate line that extends in the second direction on the second field insulating layer, the gate line overlapping the first field insulating layer along the second direction;

a gate isolation layer between the first field insulating layer and the gate line; and

gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

2. The semiconductor device as claimed in claim 1 , wherein the gate line includes:

a gate electrode including a metal, and

a gate insulating layer that extends in the second direction between the gate electrode and the second field insulating layer, and extends in a third direction between the gate electrode and the gate isolation layer.

3. The semiconductor device as claimed in claim 2 , wherein a first side surface of the gate isolation layer is in contact with a portion of the gate insulating layer between the gate electrode and the gate isolation layer.

4. The semiconductor device as claimed in claim 3 , wherein a second side surface of the gate isolation layer is in contact with a short-axial sidewall of the first field insulating layer.

5. The semiconductor device as claimed in claim 1 , wherein the gate isolation layer is in contact with the second field insulating layer.

6. The semiconductor device as claimed in claim 1 , wherein two first field insulating layers are adjacent to each other to be parallel to each other on the second filed insulating layer, and a source or drain region is between the two first field insulating layers.

7. The semiconductor device as claimed in claim 1 , wherein the first field insulating layer includes a different material from the second field insulating layer.

8. The semiconductor device as claimed in claim 7 , wherein the first field insulating layer includes silicon nitride, and the second field insulating layer includes oxide.

9. The semiconductor device as claimed in claim 1 , wherein the gate spacer includes outer gate spacers in contact with each outer sidewalls of the first field insulating layer, the gate isolation layer, and the gate line.

10. The semiconductor device as claimed in claim 1 , wherein the gate spacer includes inner gate spacers in contact with each inner sidewalls of the first field insulating layer, the gate isolation layer, and the gate line.

11. The semiconductor device as claimed in claim 1 , wherein the inner gate spacers are in contact with an upper surface of the second field insulating layer.

12. A semiconductor device, comprising:

a substrate having a first region and a second region;

first active fins that extend in a first direction in the first region;

second active fins that extend in the first direction in the second region;

a first field insulating layer between the first active fins and that extends in a second direction;

a second field insulating layer between the second active fins and extends in the second direction;

a gate line that extends in the second direction on the second field insulating layer, the gate line overlapping the first field insulating layer along the second direction;

a gate isolation layer between the first field insulating layer and the gate line; and

gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer,

wherein the gate spacer includes outer gate spacers in contact with each outer sidewalls of the first field insulating layer, the gate isolation layer, and the gate line, and the gate spacer includes inner gate spacers in contact with each inner sidewalls of the first field insulating layer, the gate isolation layer, and the gate line,

wherein one surface of the gate isolation layer is in contact with the first diffusion break region, and the other surface of the gate isolation layer is in contact with the gate line.