Semiconductor storage device

1. A semiconductor storage device, comprising:

a plurality of word lines extending in a first direction and a second direction, and separated from each other in a third direction, the first, second, and third directions crossing one another, the word lines including first, second, and third parts provided respectively in first, second, and third array regions that are arranged in the first direction;

a plurality of sense amplifier circuits partially overlapping the word lines when viewed in the third direction;

a plurality of memory strings intersecting the word lines and extending in the third direction;

a plurality of memory-side bit lines extending in the first direction and separated from each other in the second direction;

a plurality of circuit-side bit lines between the word lines and the sense amplifier circuits, the circuit-side bit lines extending in the first direction and separated from each other in the second direction, and partially overlapping the respective memory-side bit lines when viewed in the third direction;

a plurality of first contact plugs in a first connection region that is between the first and second parts of the word lines in the first direction, the first contact plugs extending in the third direction and respectively connecting a first part of the memory-side bit lines and a first part of the circuit-side bit lines; and

a plurality of second contact plugs in a second connection region that is between the second and third parts of the word lines in the first direction, the second contact plugs extending in the third direction and respectively connecting a second part of the memory-side bit lines and a second part of the circuit-side bit lines.

2. The semiconductor storage device of claim 1 , wherein

the first contact plugs are aligned in the second direction, and

the second contact plugs are aligned in the second direction.

3. The semiconductor storage device of claim 1 , wherein:

the sense amplifier circuits are located in a first circuit region, a second circuit region, a third circuit region, and a fourth circuit region arranged in the first direction;

the first part of circuit-side bit lines are electrically connected to the sense amplifier circuits that are located in the first and second circuit regions; and

the second part of circuit-side bit lines are electrically connected to the sense amplifier circuits located in the third and fourth circuit regions.

4. The semiconductor storage device of claim 3 , wherein

the first and second circuit regions are located under the second part of the word lines, and

the third and fourth circuit regions are located under the third part of the word lines.

5. The semiconductor storage device of claim 1 , wherein

each of the sense amplifier circuits includes a low voltage circuit and a high voltage circuit, and

the circuit-side bit lines are respectively connected to the high voltage circuits of the sense amplifier circuits.

6. The semiconductor storage device of claim 1 , wherein

the memory-side bit lines extend in the first direction to cross over the first part of the word lines, the first connection region, the second part of the word lines, the second connection region, and the third part of the word lines.

7. The semiconductor storage device of claim 1 , further comprising:

a plurality of third contact plugs, each connecting the first part of the circuit-side bit lines and a first part of the sense amplifier circuits; and

a plurality of fourth contact plugs, each connecting the second part of the circuit-side bit lines and a second part of the sense amplifier circuits.

8. The semiconductor storage device of claim 7 , wherein

the third contact plugs are not aligned in the second direction, and

the fourth contact plugs are not aligned in the second direction.

9. The semiconductor storage device of claim 1 , further comprising:

a plurality of data latches, each provided on the semiconductor substrate and under the word lines and connected to the sense amplifier circuits.