Precision capacitor
In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.
1. An integrated circuit, comprising:
a substrate having a first surface including active devices formed in the substrate and having an opposite second surface;
a capacitor further comprising:
a capacitor first plate comprised of a conductive material over the first surface;
a capacitor dielectric stack with silicon dioxide and silicon nitride layers on the capacitor first plate; and
a capacitor second plate comprised of a conductive material on the capacitor dielectric stack;
wherein the capacitor has a capacitance quadratic voltage coefficient with an absolute value of less than 0.5 ppm/V 2 .
2. The integrated circuit of claim 1 , wherein the silicon nitride layer has an atomic hydrogen content of less than about 25%.
3. The integrated circuit of claim 1 , wherein the capacitor has a capacitance linear voltage coefficient with an absolute value less than 3.5 ppm/V.
4. The integrated circuit of claim 1 , wherein the dielectric stack is a silicon dioxide/silicon nitride/silicon dioxide dielectric stack wherein a thickness of the silicon dioxide layers is about half a thickness of the silicon nitride layers.
5. The integrated circuit of claim 1 , wherein the integrated circuit is an analog to digital integrated circuit.
6. The integrated circuit of claim 1 , wherein the dielectric stack is a silicon nitride/silicon dioxide/silicon nitride dielectric stack and a thickness of the silicon dioxide layer is about equal to a thickness of the silicon nitride layers.
7. The integrated circuit of claim 1 , further comprising:
a premetal dielectric layer covering the capacitor.
8. The integrated circuit of claim 1 , further comprising:
an intermetal dielectric layer covering the capacitor.
9. The integrated circuit of claim 7 , wherein the first surface is silicided polysilicon.
10. The integrated circuit of claim 5 , wherein the analog to digital integrated circuit is an analog to digital converter.
11. The integrated circuit of claim 10 , wherein the analog to digital converter includes an array of the capacitors.
12. The integrated circuit of claim 8 , wherein the first surface is intermetal dielectric.
13. The integrated circuit of claim 7 , wherein the first surface is shallow trench isolation.
14. The integrated circuit of claim 1 , wherein the capacitor first plate includes cobalt silicide.