Semiconductor device including a capacitor structure with a dielectric layer structure
A semiconductor device includes a transistor disposed on a substrate; and a capacitor structure electrically connected to the transistor, wherein the capacitor structure includes a first electrode; a dielectric layer structure disposed on the first electrode; and a second electrode disposed on the dielectric layer structure, the dielectric layer structure includes an interfacial layer disposed on the first electrode; a first dielectric layer disposed on the interfacial layer and including any one of a ferroelectric material, an antiferroelectric material, and a combination of a ferroelectric material and an antiferroelectric material; an insertion layer disposed on the first dielectric layer; and a second dielectric layer disposed on the insertion layer and including a paraelectric material.
1 . A semiconductor device comprising:
a transistor disposed on a substrate; and
a capacitor structure electrically connected to the transistor,
wherein the capacitor structure comprises:
a first electrode;
a dielectric layer structure disposed on the first electrode; and
a second electrode disposed on the dielectric layer structure,
wherein the dielectric layer structure comprises:
an interfacial layer disposed on the first electrode, wherein the interfacial layer includes at least one of ruthenium oxide, titanium oxide, vanadium oxide, and molybdenum oxide;
a first dielectric layer disposed on the interfacial layer and including any one of a ferroelectric material, an antiferroelectric material, and a combination of a ferroelectric material and an antiferroelectric material;
an insertion layer disposed on the first dielectric layer, wherein the insertion layer includes at least one of aluminum oxide and silicon oxide; and
a second dielectric layer disposed on the insertion layer and including a paraelectric material, wherein the first electrode, the interfacial layer, the first dielectric layer, the insertion layer, the second dielectric layer, and the second electrode are sequentially disposed in a direction from the first electrode to the second electrode.
2 . The semiconductor device of claim 1 ,
wherein the first dielectric layer has a negative capacitance, and
the second dielectric layer has a positive capacitance.
3 . The semiconductor device of claim 1 , wherein the first dielectric layer includes at least one of HfZrO 2 , ZrO 2 , PbTiO 3 , and AgNbO 3 .
4 . The semiconductor device of claim 1 , wherein a conductive band offset between the insertion layer and the first dielectric layer is 5 eV or more.
5 . The semiconductor device of claim 4 , wherein the first dielectric layer comprises a first thickness in a first direction perpendicular to an upper surface of the first electrode, and the second dielectric layer comprises a second thickness in the first direction, and the first thickness is greater than second thickness.
6 . The semiconductor device of claim 1 , wherein the second dielectric layer includes at least one of HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 3 , VO 2 , AlO 2 , SiO 2 , SrTiO 3 BaTiO 3 , and BiFeO 3 .
7 . The semiconductor device of claim 6 ,
wherein the second dielectric layer further includes not more than 5 atomic percent of a first dopant, and
the first dopant includes at least one of zirconium, silicon, titanium, yttrium, aluminum, lanthanum, and gadolinium.
8 . The semiconductor device of claim 1 , wherein the insertion layer has a thickness of 5 Å or more.
9 . The semiconductor device of claim 1 ,
wherein the first dielectric layer has a first thickness in a first direction perpendicular to an upper surface of the first electrode, the first thickness being 40 angstroms (Å) to 55 Å,
the second dielectric layer has a second thickness in the first direction, the second thickness being 5 Å to 20 Å, and
the dielectric layer structure has a third thickness in the first direction, the third thickness being 50 Å to 70 Å.
10 . The semiconductor device of claim 1 , wherein the dielectric layer structure exhibits at least one capacitance-voltage characteristic which shows a behavior of a first-order function in a positive driving voltage region and shows a behavior of a second-order function in a negative driving voltage region.
11 . The semiconductor device of claim 10 ,
wherein the positive driving voltage region is a region of 0 to 1 V, and
the negative driving voltage region is a region of −1 to 0 V.
12 . The semiconductor device of claim 11 ,
wherein the dielectric layer structure exhibits a first capacitance-voltage characteristic based on Equation 1 in the positive driving voltage region and exhibits a second capacitance-voltage characteristic based on Equation 2 in the negative driving voltage region,
f ( x )= a 1 x+b 1, [Equation 1]
f ( x )= a 2( x−c )2+ b 2, [Equation 2]
where a1, a2, b1, b2, and c are constants, and a1>0 and a2<0.
13 . The semiconductor device of claim 1 , wherein the second dielectric layer is in direct contact with the second electrode.
14 . A semiconductor device comprising:
a transistor disposed on a substrate; and
a capacitor structure electrically connected to the transistor,
wherein the capacitor structure includes a first electrode, a second electrode, and a dielectric layer structure interposed between the first electrode and the second electrode,
wherein the dielectric layer structure comprises:
an interfacial layer disposed on the first electrode;
a first dielectric layer disposed on the interfacial layer and including a first dielectric material having a negative capacitance;
an insertion layer disposed on the first dielectric layer; and
a second dielectric layer disposed on the insertion layer and including a second dielectric material having a positive capacitance, wherein a conductive band offset between the insertion layer and the first dielectric layer is 5 eV or more, and wherein the first electrode, the interfacial layer, the first dielectric layer, the insertion layer, the second dielectric layer, and the second electrode are sequentially disposed in a direction from the first electrode to the second electrode.
15 . The semiconductor device of claim 14 ,
wherein the dielectric layer structure exhibits at least one capacitance-voltage characteristic which shows a behavior of a first-order function in a positive driving voltage region and shows a behavior of a second-order function in a negative driving voltage region,
the positive driving voltage region is a region of 0 to 1 V, and
the negative driving voltage region is a region of −1 to 0 V.
16 . The semiconductor device of claim 15 ,
wherein the dielectric layer structure exhibits a first capacitance-voltage characteristic based on Equation 1 in the positive driving voltage region and exhibits a second capacitance-voltage characteristic based on Equation 2 in the negative driving voltage region,
f ( x )= a 1 x+b 1, [Equation 1]
f ( x )= a 2( x−c )2+ b 2, [Equation 2]
where a1, a2, b1, b2, and c are constants, and a1>0 and a2<0.
17 . The semiconductor device of claim 14 , wherein the first dielectric layer includes any one of a ferroelectric material, an antiferroelectric material, and a combination of a ferroelectric material and an antiferroelectric material, and
the second dielectric layer includes a paraelectric material.
18 . The semiconductor device of claim 14 ,
wherein the first dielectric layer includes at least one of HfZrO 2 , ZrO 2 , PbTiO 3 , and AgNbO 3 , and
the second dielectric layer includes at least one of HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 3 , VO 2 , AlO 2 , SiO 2 , SrTiO 3 BaTiO 3 , and BiFeO 3 .
19 . The semiconductor device of claim 18 ,
wherein the second dielectric layer further comprises not more than 5 atomic percent of a first dopant, and
the first dopant includes at least one of zirconium, silicon, titanium, yttrium, aluminum, lanthanum, and gadolinium.
20 . A semiconductor device comprising:
a word line arranged in a word line trench extending in a first direction within a substrate;
a contact structure disposed on one side of the word line on the substrate; and
a capacitor structure disposed on the contact structure and electrically connected to the contact structure,
wherein the capacitor structure comprises:
a first electrode disposed on the contact structure;
a dielectric layer structure covering the first electrode; and
a second electrode disposed on the dielectric layer structure, and
wherein the dielectric layer structure comprises:
an interfacial layer disposed on the first electrode;
a first dielectric layer disposed on the interfacial layer and including any one of a ferroelectric material, an antiferroelectric material, and a combination of a ferroelectric material and an antiferroelectric material, wherein the first dielectric layer has a first thickness in a second direction perpendicular to an upper surface of the first electrode;
an insertion layer disposed on the first dielectric layer; and
a second dielectric layer disposed on the insertion layer and including a paraelectric material, the second dielectric layer being in direct contact with the second electrode, wherein the second dielectric layer has a second thickness in the second direction, and wherein the second thickness is less than half of the first thickness.