Hybrid cascode constructions with multiple transistor types
Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.
1. A structure comprising:
a field-effect transistor including a gate electrode finger, a first source/drain region, and a second source/drain region; and
a bipolar junction transistor including a first terminal, a base layer with an intrinsic base portion on the first terminal, and a second terminal that includes one or more fingers on the intrinsic base portion of the base layer, the intrinsic base portion of the base layer arranged in a vertical direction between the first terminal and the second terminal,
wherein the first source/drain region is coupled with the first terminal, the first source/drain region at least partially surrounds the bipolar junction transistor, the field-effect transistor is arranged in an input stage of a cascode amplifier circuit, and the bipolar junction transistor is arranged in an output stage of the cascode amplifier circuit.
2. The structure of claim 1 wherein the first source/drain region is a drain region of the field-effect transistor, the first terminal is an emitter of the bipolar junction transistor, and the drain region and the emitter are formed in a device layer of a silicon-on-insulator substrate.
3. The structure of claim 2 further comprising:
a dielectric isolation region extending vertically in the device layer to a buried oxide layer of the silicon-on-insulator substrate, the dielectric isolation region arranged between the drain region and the emitter.
4. The structure of claim 1 wherein the bipolar junction transistor is a heterojunction bipolar transistor.
5. The structure of claim 1 wherein the first source/drain region is directly coupled with the first terminal.
6. The structure of claim 1 further comprising:
a dielectric isolation region arranged between the first source/drain region and the first terminal.
7. The structure of claim 6 further comprising:
a passive device element coupled with the first source/drain region and with the first terminal.
8. The structure of claim 1 wherein the first source/drain region is a source region of the field-effect transistor, the first terminal is a collector of the bipolar junction transistor, and the source region and the collector are formed in a device layer of a silicon-on-insulator substrate.
9. The structure of claim 1 wherein the first source/drain region and the second source/drain region each extend vertically in a device layer of a silicon-on-insulator substrate to intersect with a buried oxide layer of the silicon-on-insulator substrate.
10. The structure of claim 1 wherein the first source/drain region and the first terminal are formed in a device layer of a silicon-on-insulator substrate.
11. The structure of claim 1 wherein the bipolar junction transistor and the field-effect transistor are formed in a bulk substrate.
12. The structure of claim 1 wherein the first source/drain region completely surrounds the bipolar junction transistor.
13. The structure of claim 1 wherein the gate electrode finger and the second source/drain region completely surround the bipolar junction transistor, and the first source/drain region is arranged between the gate electrode finger and the bipolar junction transistor.
14. The structure of claim 1 wherein the first source/drain region partially surrounds the bipolar junction transistor with one or more discontinuities breaking the first source/drain region into a first section and a second section, and further comprising:
one or more trench isolation regions located in the one or more discontinuities.
15. A method comprising:
forming a field-effect transistor that includes a gate electrode finger, a first source/drain region, and a second source/drain region; and
forming a bipolar junction transistor that includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer,
wherein the intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal, the first source/drain region is coupled with the first terminal, the first source/drain region at least partially surrounds the bipolar junction transistor, the field-effect transistor is arranged in an input stage of a cascode amplifier circuit, and the bipolar junction transistor is arranged in an output stage of the cascode amplifier circuit.