IP Library Granted Patent US 10,651,146
Granted Patent B2
US 10,651,146 · App. 13/606,147 · Granted May 12, 2020

Chip packaging structure and manufacturing method for the same

Inventor: Diann-Fang Lin (Miao-Li, TW)
Assignee: Dawning Leading Technology Inc.
H01L25/0652H01L23/4951H01L23/49503H01L23/49531H01L23/49565H01L23/49575H01L23/49833H01L23/49838H01L24/49H01L25/0655H01L25/16H01L23/3121H01L23/49816H01L24/32H01L24/48H01L24/73H01L2223/6677H01L2224/0401H01L2224/04042H01L2224/06155H01L2224/16145H01L2224/16225H01L2224/32145H01L2224/32225H01L2224/4824H01L2224/48137H01L2224/48145H01L2224/48147H01L2224/48157H01L2224/48227H01L2224/48247H01L2224/73207H01L2224/73215H01L2224/73265H01L2225/0651H01L2225/06506H01L2225/06562H01L2225/06568H01L2924/00014H01L2924/15311H01L2924/19041H01L2924/19042H01L2924/19104H01L2924/19107
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Quick Facts
Patent No.
US 10,651,146
App. No.
13/606,147
Granted
May 12, 2020
Kind
B2
Abstract

A chip packaging structure and a manufacturing method for the same are provided. The chip packaging structure includes a first chip, a second chip and a transfer component. The first chip has a plurality of first bonding pads formed on the top surface of the first chip. The second chip has a plurality of second bonding pads formed on the top surface of the second chip. The first chip and the second chip are arranged abreast and electrically connected to each other. The transfer component is disposed on the top surface of the first chip and electrically connected with the first chip. Via these arrangements, the chip packaging structure can have smaller dimensions.

Claims (20)

1. A chip packaging structure, comprising:

a first chip, having a plurality of first bonding pads formed on a top surface of the first chip;

a second chip, having a plurality of second bonding pads formed on a top surface of the second chip, wherein the first chip and the second chip are arranged abreast and electrically connected with each other;

a transfer component, disposed on the top surface of the first chip and electrically connected with the first chip, and wherein the transfer component has a plurality of third bonding pads formed on a top surface of the transfer component, and one of the first bonding pads is wire bonded to a leftmost one of the third bonding pads which is electrically connected to a rightmost one of the third bonding pads;

a plurality of metal pins which are arranged abreast of the second chip, wherein the metal pins are electrically connected with the first chip and the second chip, wherein the second chip is located between the metal pins and the first chip along a first direction, and the first bonding pads, the leftmost one and the rightmost one of the third bonding pads and the second bonding pads are arranged sequentially along the first direction; and

an encapsulation material which encapsulates the first chip, the second chip, the transfer component and the metal pins, wherein each of the metal pins has a surface exposed from the encapsulation material, and wherein bottom surfaces of the first chip and the second chip are directly contacted by the encapsulation material without an adhesion layer disposed thereon;

wherein one of the metal pins is wire bonded to the rightmost one of the third bonding pads of the transfer component, so that an electrical signal from the first chip is transmitted to the metal pins through the transfer component where the electrical signal is transmitted from the leftmost one to the rightmost one of the third bonding pads along the first direction.

2. The structure of claim 1 , wherein one of the second bonding pads is wire bonded to the rightmost one of the third bonding pads.

3. The structure of claim 1 , wherein the transfer component is further disposed on the top surface of the second chip, and is electrically connected with the second chip.

4. The structure of claim 1 , further comprising an adhesion layer which is disposed between the top surface of the first chip and the transfer component so as to adhere the transfer component onto the top surface of the first chip.

5. A method for producing a chip packaging structure, comprising steps of:

providing a first chip which has a plurality of first bonding pads formed on a top surface of the first chip;

providing a second chip which has a plurality of second bonding pads formed on a top surface of the second chip;

arranging the first chip and the second chip abreast, and electrically connecting the first chip with the second chip;

placing a transfer component on the top surface of the first chip, and electrically connecting the transfer component with the first chip and/or the second chip, wherein the transfer component has a plurality of third bonding pads formed on a top surface of the transfer component, one of the first bonding pads is wire bonded to a leftmost one of the third bonding pads which is electrically connected to a rightmost one of the third bonding pads;

arranging a plurality of metal pins abreast of the second chip, and then electrically connecting the metal pins with the first chip and the second chip, wherein the second chip is located between the metal pins and the first chip along a first direction, and the first bonding pads, the leftmost one and the rightmost one of the third bonding pads and the second bonding pads are arranged sequentially along the first direction; and

using an encapsulation material to encapsulate the first chip, the second chip, the transfer component and the metal pins, wherein each of the metal pins has a surface exposed from the encapsulation material and bottom surfaces of the first chip and the second chip are directly contacted by the encapsulation material without an adhesion layer disposed thereon;

wherein one of the metal pins is wire bonded to the rightmost one of the third bonding pads of the transfer component, so that an electrical signal from the first chip is transmitted to the metal pins through the transfer component where the electrical signal is transmitted from the leftmost one to the rightmost one of the third bonding pads along the first direction.

6. The method of claim 5 , further comprising steps of: placing the transfer component on the top surface of the second chip, and electrically connecting the transfer component with the second chip.

7. The method of claim 5 , further comprising steps of: disposing an adhesion layer on the top surface of the first chip; and placing the transfer component on the adhesion layer so as to adhere the transfer component onto the top surface of the first chip.

Assignments (2)
MERGER Recorded Dec 15, 2020
From: DAWNING LEADING TECHNOLOGY INC.
To: KING YUAN ELECTRONICS CO., LTD.
Reel/Frame 054754/0255 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2012
From: LIN, DIANN-FANG
To: DAWNING LEADING TECHNOLOGY INC.
Reel/Frame 028913/0089 →
Priority Claims (1)
TW 100132669 A · Sep 9, 2011 · national
Continuity (1)
Related Publication 20130062783A1 · Mar 14, 2013