Three-dimensional memory devices and methods for forming the same
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device.
1. A three-dimensional (3D) memory device, comprising:
a substrate;
a peripheral device comprising a multiplexer disposed on the substrate;
a first memory stack disposed above the peripheral device;
a first memory string extending vertically through the first memory stack;
a first bit line disposed above and electrically connected to the first memory string and the multiplexer, wherein the first bit line is electrically connected to a first drain at an upper end of the first memory string;
a second memory stack disposed above the first bit line;
a second memory string extending vertically through the second memory stack; and
a second bit line disposed above and electrically connected to the second memory string and the multiplexer, wherein the second bit line is electrically connected to a second drain at an upper end of the second memory string,
wherein the multiplexer is electrically connected to the first and second memory strings as inputs, and the multiplexer is configured to select one of the first and second memory strings to be forwarded through the multiplexer.
2. The 3D memory device of claim 1 , wherein the peripheral device further comprises a data buffer and a driver electrically connected to an output of the multiplexer and shared by the first and second memory strings through the multiplexer.
3. The 3D memory device of claim 1 , further comprising:
a peripheral interconnect layer disposed above the peripheral device;
a first source plate disposed between the peripheral interconnect layer and the first memory stack and that is electrically connected to the peripheral interconnect layer; and
a second source plate disposed between the first bit line and the second memory stack and that is electrically connected to the peripheral interconnect layer.
4. The 3D memory device of claim 3 , wherein each of the first and second source plates comprises:
a conductive plate electrically connected to the peripheral interconnect layer; and
a semiconductor plate disposed on the conductive plate and in contact with a lower end of a respective first or second memory string.
5. The 3D memory device of claim 4 , wherein the conductive plate comprises metal silicide, and the semiconductor plate comprises polysilicon.
6. A three-dimensional (3D) memory device, comprising:
a substrate;
a peripheral device disposed on the substrate;
a first memory stack disposed above the peripheral device;
a first memory string extending vertically through the first memory stack;
a first bit line disposed above and electrically connected to the first memory string and the peripheral device, wherein the first bit line is electrically connected to a first drain at an upper end of the first memory string;
a second memory stack disposed above the first bit line;
a second memory string extending vertically through the second memory stack;
a second bit line disposed above and electrically connected to the second memory string and the peripheral device, wherein the second bit line is electrically connected to a second drain at an upper end of the second memory string;
a third memory stack disposed above the second bit line;
a third memory string extending vertically through the third memory stack; and
a third bit line disposed above and electrically connected to the third memory string and the peripheral device, wherein the third bit line is electrically connected to a third drain at an upper end of the third memory string.
7. The 3D memory device of claim 6 , wherein the peripheral device comprises a multiplexer electrically connected to the first, second, and third memory strings as inputs, and configured to select one of the first, second, and third memory strings to be forwarded through the multiplexer.
8. The 3D memory device of claim 7 , wherein the peripheral device further comprises a data buffer and a driver electrically connected to an output of the multiplexer and shared by the first, second, and third memory strings through the multiplexer.
9. The 3D memory device of claim 6 , further comprising:
a peripheral interconnect layer disposed above the peripheral device;
a first source plate disposed between the peripheral interconnect layer and the first memory stack and that is electrically connected to the peripheral interconnect layer; and
a second source plate disposed between the first bit line and the second memory stack and that is electrically connected to the peripheral interconnect layer.
10. The 3D memory device of claim 9 , wherein each of the first and second source plates comprises:
a conductive plate electrically connected to the peripheral interconnect layer; and
a semiconductor plate disposed on the conductive plate and in contact with a lower end of a respective first or second memory string.
11. The 3D memory device of claim 10 , wherein the conductive plate comprises metal silicide, and the semiconductor plate comprises polysilicon.
12. The 3D memory device of claim 9 , further comprising:
a third source plate disposed between the second bit line and the third memory stack and that is electrically connected to the peripheral interconnect layer.