IP Library Granted Patent US 10,658,277
Granted Patent B2
US 10,658,277 · App. 16/057,792 · Granted May 19, 2020

Semiconductor package with a heat spreader and method of manufacturing thereof

Inventors: Antonio Bambalan Dimaano, Jr. (Singapore, SG); Nataporn Charusabha (Bangkok, TH); Saravuth Sirinorakul (Bangkok, TH); Preecha Joymak (Bangkok, TH); Roel Adeva Robles (Singapore, SG)
Assignee: UTAC Headquarters Pte. Ltd.
H01L23/49568H01L21/4825H01L21/4875H01L23/3121H01L23/4334H01L23/49524H01L23/49548H01L24/40H01L23/3107H01L23/49513H01L24/03H01L24/05H01L24/06H01L24/29H01L24/32H01L24/45H01L24/48H01L24/73H01L24/92H01L2224/0345H01L2224/04026H01L2224/04042H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/06181H01L2224/2919H01L2224/2929H01L2224/29339H01L2224/32245H01L2224/40245H01L2224/40247H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/48247H01L2224/48257H01L2224/48465H01L2224/73221H01L2224/73263H01L2224/73265H01L2224/92246H01L2224/92247H01L2224/94H01L2224/97H01L2924/13091
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Quick Facts
Patent No.
US 10,658,277
App. No.
16/057,792
Granted
May 19, 2020
Kind
B2
Abstract

Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.

Claims (32)

1. A semiconductor package comprising:

a package substrate comprising a top substrate surface and a bottom substrate surface, wherein the package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface;

a heat spreader disposed on the top substrate surface, the heat spreader comprises a top planar surface and a bottom planar surface, wherein the top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region, wherein the heat spreader comprises a thickness extending from the top planar surface the bottom planar surface;

a semiconductor die, wherein the semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region;

wherein the package substrate is a lead frame comprising a die-attach paddle and a plurality of lead fingers peripherally located relative to the die-attach paddle, wherein the heat spreader is directly disposed on a top surface of the die-attach paddle; and

wherein the thickness of the heat spreader is greater relative to the thickness of the package substrate.

2. The semiconductor package of claim 1 wherein the heat spreader covers the entire top surface of the die-attach paddle without extending beyond the die-attach paddle.

3. The semiconductor package of claim 1 wherein the heat spreader and the lead frame comprises copper material.

4. The semiconductor package of claim 1 comprising wire bonds, wherein the wire bonds electrically connect the semiconductor die to the plurality of lead fingers.

5. The semiconductor package of claim 1 comprising a metal clip structure, wherein the metal clip structure electrically connect the semiconductor die to the plurality of lead fingers.

6. The semiconductor package of claim 1 wherein the heat spreader and the die-attach paddle collectively corresponds to a heat sink element having a thickness substantially equal to 20 mils.

7. The semiconductor package of claim 1 comprising an encapsulant structure, wherein the encapsulant structure encapsulates at least the semiconductor die and the heat spreader, wherein the encapsulant structure covers and contacts the non-die region and sidewalls of the heat spreader.

8. A semiconductor package comprising:

a lead frame, the lead frame comprises a die-attach paddle and a plurality of lead fingers peripherally located relative to the die-attach paddle, wherein the die-attach paddle comprises a thickness extending from a top planar surface to a bottom planar surface of the die-attach paddle;

a heat spreader disposed on the top planar surface of the die-attach paddle, the heat spreader comprises a top planar surface and a bottom planar surface, wherein the top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region, wherein the heat spreader comprises a thickness extending from the top planar surface to the bottom planar surface of the heat spreader;

a semiconductor die, wherein the semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region; and

wherein the thickness of the heat spreader is greater relative to the thickness of the die-attach paddle.

9. The semiconductor package of claim 8 comprising an encapsulant structure, wherein the encapsulant structure encapsulates at least the semiconductor die and the heat spreader, wherein the encapsulant structure covers and contacts the non-die region and sidewalls of the heat spreader.

10. The semiconductor package of claim 9 wherein the heat spreader covers the entire top surface of the die-attach paddle without extending beyond the die-attach paddle.

11. The semiconductor package of claim 9 wherein the heat spreader and the lead frame comprises copper material.

12. The semiconductor package of claim 9 comprising wire bonds, wherein the wire bonds electrically connect the semiconductor die to the plurality of lead fingers.

13. The semiconductor package of claim 9 comprising a metal clip structure, wherein the metal clip structure electrically connect the semiconductor die to the plurality of lead fingers.

14. The semiconductor package of claim 8 comprising an electrically and thermally conductive adhesive layer disposed directly between the semiconductor die and the heat spreader.

15. A semiconductor package comprising:

a lead frame, wherein the lead frame comprises a die-attach paddle and a plurality of lead fingers peripherally located relative to the die-attach paddle, wherein the die-attach paddle comprises a thickness extending from a top planar surface to a bottom planar surface of the die-attach paddle;

a heat spreader, wherein the heat spreader is coupled to the top planar surface of the die-attach paddle, the heat spreader comprises a top planar surface and a bottom planar surface, wherein the top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region, wherein the heat spreader comprises a thickness extending from the top planar surface to the bottom planar surface of the heat spreader;

a semiconductor die, wherein the semiconductor die is mounted to the top planar surface of the heat spreader in the die region, wherein the heat spreader is sandwiched between the semiconductor die and the die-attach paddle; and

wherein the thickness of the heat spreader is greater relative to the thickness of the die-attach paddle.

16. The semiconductor package of claim 15 wherein the heat spreader and the die-attach paddle comprise a same metal material.

17. The semiconductor package of claim 15 comprises an encapsulant structure, wherein the encapsulant structure encapsulates at least the semiconductor die and the heat spreader, wherein the encapsulant structure covers and contacts the non-die region and sidewalls of the heat spreader.

18. The semiconductor package of claim 15 wherein the heat spreader covers entirely the top planar surface of the die-attach paddle without extending beyond the die-attach paddle.

19. The semiconductor package of claim 15 comprising wire bonds, wherein the wire bonds electrically connect the semiconductor die to the plurality of lead fingers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2020
From: DIMAANO JR., ANTONIO BAMBALAN; CHARUSABHA, NATAPORN; SIRINORAKUL, SARAVUTH; JOYMAK, PREECHA; ROBLES, ROEL ADEVA
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 052326/0219 →
Continuity (2)
Provisional Application 62542308 · Aug 8, 2017
Related Publication 20190051585A1 · Feb 14, 2019