IP Library › Granted Patent US 10,658,467
Granted Patent B2
US 10,658,467 · App. 16/284,012 · Granted May 19, 2020

Semiconductor device

Inventor: Yoichi Hori (Hyogo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L29/1608H01L29/0615H01L29/0692H01L29/43H01L29/868H01L29/41
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Quick Facts
Patent No.
US 10,658,467
App. No.
16/284,012
Granted
May 19, 2020
Kind
B2
Abstract

A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane; a first silicon carbide region of a first conductivity type in the silicon carbide layer; a second silicon carbide region of a second conductivity type between the first silicon carbide region and the first plane; a third silicon carbide region of the second conductivity type between the first silicon carbide region and the first plane, the third silicon carbide region extending in a first direction parallel to the first plane; a first electrode provided on a side of the first plane; a second electrode provided on a side of the second plane; and a metal silicide layer provided between the first electrode and the second silicon carbide region, the metal silicide layer having a portion being in contact with the first plane, and a shape of the portion being an octagon.

Claims (17)

1. A semiconductor device comprising:

a silicon carbide layer having a first plane and a second plane facing the first plane;

a first silicon carbide region of a first conductivity type provided in the silicon carbide layer;

a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first plane;

a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first plane, the third silicon carbide region extending in a first direction parallel to the first plane, the third silicon carbide region being connected to the second silicon carbide region, and the third silicon carbide region having a first width in a second direction, the second direction being parallel to the first plane and perpendicular to the first direction, the first width being narrower than a second width of the second silicon carbide region in the second direction;

a first electrode provided on a side of the first plane of the silicon carbide layer and the first electrode being in contact with the first silicon carbide region;

a second electrode provided on a side of the second plane of the silicon carbide layer; and

a metal silicide layer provided between the first electrode and the second silicon carbide region, the metal silicide layer having a portion being in contact with the first plane, and a shape of the portion being an octagon.

2. The semiconductor device according to claim 1 , wherein at least one side among eight sides of the octagon is parallel to the first direction.

3. The semiconductor device according to claim 1 , further comprising a fourth silicon carbide region of the second conductive type provided between the second silicon carbide region and the metal silicide layer, and the fourth silicon carbide region having a second conductive type impurity concentration higher than a second conductive type impurity concentration of the second silicon carbide region.

4. The semiconductor device according to claim 1 , wherein the metal silicide layer contains nickel silicide or titanium silicide.

5. The semiconductor device according to claim 1 , wherein the first conductivity type is an n type and the second conductivity type is a p type.

6. The semiconductor device according to claim 1 , further comprising a fifth silicon carbide region of the first conductivity type provided between the first silicon carbide region and the second plane, and the fifth silicon carbide region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region.

7. The semiconductor device according to claim 1 , wherein a first conductivity type impurity concentration of the first silicon carbide region is 1×10 14 cm −3 or higher and 2×10 16 cm −3 or lower.

8. The semiconductor device according to claim 1 , wherein a second conductivity type impurity concentration of the second silicon carbide region is 1×10 14 cm −3 or higher and 5×10 18 cm −3 or lower.

9. The semiconductor device according to claim 1 , wherein a second conductivity type impurity concentration of the third silicon carbide region is 5×10 16 cm −3 or higher and 5×10 18 cm −3 or lower.

10. The semiconductor device according to claim 1 , wherein a second conductivity type impurity concentration of the fourth silicon carbide region is 1×10 19 cm −3 or higher and 1×10 21 cm −3 or lower.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2019
From: HORI, YOICHI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 048422/0318 →
Priority Claims (1)
JP 2018-175441 · Sep 19, 2018 · national
Continuity (1)
Related Publication 20200091298A1 · Mar 19, 2020
Cited By (1)
US 12,622,040