Fin cut last method for forming a vertical FinFET device
A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric.
1. A vertical FinFET structure, comprising:
a pair of fins disposed over a semiconductor substrate;
a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of each fins is in contact with the bottom source/drain region;
a bottom spacer disposed over the bottom source/drain region;
a gate stack disposed over sidewalls of the fins, the gate stack extending laterally over the bottom spacer on opposing sides of each fin;
a top spacer disposed over the gate stack;
a first dielectric layer disposed over the top spacer;
a top source/drain region disposed over an upper portion of each of the fins; and
an isolation structure comprising an isolation dielectric layer disposed between the pair of fins, wherein the isolation structure includes a lower portion having a first width that extends vertically through the bottom spacer into the substrate and between the bottom source/drain region of each fin, and a middle portion above a bottom portion, wherein the middle portion extends laterally over the bottom spacer and has a second width greater than the first width.
2. The vertical FinFET structure of claim 1 , wherein the gate stack and the top spacer are disposed between each fin and the middle portion of the isolation structure.
3. The vertical FinFET structure of claim 1 , wherein the isolation structure comprises a nitride liner disposed between the isolation dielectric layer and each of the top spacer and the bottom spacer.
4. The vertical FinFET structure of claim 3 , wherein the nitride liner is disposed over respective vertical surfaces of the first dielectric layer, the top spacer and the bottom spacer.
5. The vertical FinFET structure of claim 1 , further comprising a shallow trench isolation layer disposed within the semiconductor substrate beneath the middle portion of the isolation structure.
6. The vertical FinFET structure of claim 5 , wherein the lower portion of the isolation structure extends completely through the shallow trench isolation layer.
7. The vertical FinFET structure of claim 5 , wherein the first dielectric layer, the isolation dielectric layer and the shallow trench isolation layer each comprise silicon dioxide.
8. The vertical FinFET structure of claim 1 , wherein the middle portion of the isolation structure comprises an air-gap.
9. The vertical FinFET structure of claim 1 , wherein the isolation structure further comprises a top portion above the middle portion having a third width less than the second width.
10. A vertical field effect transistor (FET) structure, comprising:
a pair of active semiconductor regions disposed over a semiconductor substrate;
a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of each active semiconductor region is in contact with the bottom source/drain region;
a bottom spacer disposed over the bottom source/drain region;
a gate stack disposed over sidewalls of the active semiconductor regions, the gate stack extending laterally over the bottom spacer on opposing sides of each active semiconductor region;
a top spacer disposed over the gate stack;
a first dielectric layer disposed over the top spacer;
a top source/drain region disposed over an upper portion of each of the active semiconductor regions; and
an isolation structure comprising an isolation dielectric layer disposed between the pair of active semiconductor regions, wherein the isolation structure includes a lower portion having a first width that extends vertically through the bottom spacer into the substrate and between the bottom source/drain region of each active semiconductor region, and a middle portion above a bottom portion, wherein the middle portion extends laterally over the bottom spacer and has a second width greater than the first width.
11. The vertical FET structure of claim 10 , further comprising a shallow trench isolation layer disposed within the semiconductor substrate beneath the middle portion of the isolation structure.
12. A vertical field effect transistor (FET) structure, comprising:
a pair of active semiconductor regions disposed over a semiconductor substrate;
a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of each active semiconductor region is in contact with the bottom source/drain region;
a bottom spacer disposed over the bottom source/drain region;
a gate stack disposed over sidewalls of the active semiconductor regions, the gate stack extending laterally over the bottom spacer on opposing sides of each active semiconductor region,
a top spacer disposed over the gate stack;
a first dielectric layer disposed over the top spacer;
a top source/drain region disposed over an upper portion of each of the active semiconductor regions;
a nitride liner disposed between the isolation dielectric layer and each of the top spacer and the bottom spacer, and between the pair of active semiconductor regions, wherein the nitride liner includes a lower portion having a first width that extends vertically through the bottom spacer into the substrate and between the bottom source/drain region of each active semiconductor region, and a middle portion above the bottom portion, wherein the middle portion extends laterally over the bottom spacer and has a second width greater than the first width; and
a shallow trench isolation layer disposed within the semiconductor substrate beneath the middle portion of the isolation structure.
13. The vertical FET structure of claim 12 , wherein the nitride liner is disposed over respective vertical surfaces of the first dielectric layer, the top spacer and the bottom spacer.
14. The vertical FET structure of claim 12 , wherein the lower portion of the nitride liner extends completely through the shallow trench isolation layer.
15. The vertical FET structure of claim 12 , wherein the middle portion of the nitride liner includes an air-gap.
16. The vertical FET structure of claim 12 , wherein the nitride liner further comprises a top portion above the middle portion having a third width less than the second width.