Memory device with channel discharge before program-verify based on data state and sub-block position
Techniques are disclosed for reducing an injection type of read disturb in a memory device. During a program loop, when NAND strings in a selected sub-block are programmed, a pre-verify voltage pulse is applied to a selected word line and to a select gate transistor to discharge the drain-side channel in NAND strings of unselected sub-blocks. The duration of the pulse can vary for the different unselected sub-blocks and can be based on a sub-block programming order. In another aspect, the duration is higher for initial program loops in a program operation, when lower data states are being verified, and then decreases to a lower level for subsequent program loops when higher data states are being verified.
1. An apparatus, comprising:
a set of memory cells arranged in NAND strings in a block, each NAND string has a drain-end and a source end, and a select gate transistor at the drain-end;
a selected word line and unselected word lines connected to the set of memory cells; and
a control circuit, the control circuit, to program memory cells connected to the selected word line in a selected sub-block of the block, is configured to:
apply a program pulse to the selected word line;
after the applying of the program pulse, increase voltages of the unselected word lines to pass voltages;
apply a pre-verify voltage pulse to select gate transistors in one programmed unselected sub-block of the block, wherein the applying of the pre-verify voltage pulse to the select gate transistors in the one programmed unselected sub-block is concurrent with the increase of the voltages of the unselected word lines, and a duration of the pre-verify voltage pulse is a function of a sub-block programming order of the block; and
after the pre-verify voltage pulse, apply a verify voltage to the selected word line.
2. The apparatus of claim 1 , wherein:
the control circuit is configured to apply a pre-verify voltage pulse to the selected word line concurrently with the applying of the pre-verify voltage pulse to the select gate transistors in the one programmed unselected sub-block.
3. The apparatus of claim 1 , wherein:
the duration is relatively longer when a number of sub-blocks in the block which are programmed after the one programmed unselected sub-block and before the selected sub-block is relatively larger.
4. The apparatus of claim 1 , wherein:
the control circuit is configured to apply a pre-verify voltage pulse to select gate transistors in another programmed unselected sub-block of the block concurrent with the increase of the voltages of the unselected word lines; and
a duration of the pre-verify voltage pulse for the another programmed unselected sub-block is less than the duration of the pre-verify voltage pulse for the one programmed unselected sub-block when the another programmed unselected sub-block is programmed after the one programmed unselected sub-block.
5. The apparatus of claim 1 , wherein:
the verify voltage is among a plurality of verify voltages which are applied successively to the selected word line; and
the duration is a function of a first verify voltage of the plurality of verify voltages.
6. The apparatus of claim 1 , wherein:
the memory cells connected to the selected word line in the selected sub-block are assigned to a plurality of data states;
the plurality of data states are arranged in groups; and
the duration is a function of one of the groups which is associated with the verify voltage.
7. The apparatus of claim 1 , wherein:
the duration is relatively longer when the verify voltage is relatively lower.
8. The apparatus of claim 1 , wherein:
the control circuit is configured to apply a pre-verify voltage pulse to select gate transistors of an unprogrammed unselected sub-block of the block concurrent with the increase of the voltages of the unselected word lines; and
a duration of the pre-verify voltage pulse applied to the select gate transistors of the unprogrammed unselected sub-block is less than the duration of the pre-verify voltage pulse applied to the select gate transistors of the one programmed unselected sub-block.
9. The apparatus of claim 1 , wherein:
during the increase of the voltages of the unselected word lines, the control circuit is configured to apply a turn-off voltage to select gate transistors of an unprogrammed unselected sub-block of the block.
10. The apparatus of claim 1 , wherein:
the memory cells connected to the selected word line are programmed in a single-pass program operation;
the unselected word lines comprise source-side word lines of the selected word line and drain-side word lines of the selected word line;
the pass voltages comprise a pass voltage for the source-side word lines and a pass voltage for the drain-side word lines; and
the pass voltage for the drain-side word lines is less than the pass voltage for the source-side word lines.
11. The apparatus of claim 1 , wherein:
memory cells connected to an adjacent drain-side word line of the selected word line are programmed before the programming of the memory cells connected to the selected word line;
the unselected word lines comprise the adjacent drain-side word line and remaining drain-side word lines;
the pass voltages comprise a pass voltage for the adjacent drain-side word line and a pass voltage for the remaining drain-side word lines; and
the pass voltage for the remaining drain-side word lines is less than the pass voltage for the adjacent drain-side word line.
12. The apparatus of claim 1 , wherein:
the programming of the memory cells connected to the selected word line in the selected sub-block occurs in a foggy programming pass of a foggy-fine multi-pass program operation.
13. A method, comprising:
applying a program pulse to a selected word line in a set of word lines, the set of word lines are connected to a set of memory cells arranged in NAND strings in a block, each NAND string has a drain-end and a source end, and a select gate transistor at the drain-end and the program pulse is part of a program operation for memory cells connected to the selected word line in a selected sub-block;
after the applying of the program pulse, performing a channel boosting operation for NAND strings in an unselected sub-block of the block, the performing the channel boosting operation comprises increasing voltages of unselected word lines in the set of word lines to pass voltages and applying a pre-verify voltage pulse to the selected word line and to select gate transistors in an unselected sub-block; and
after the performing of the channel boosting operation, applying a verify voltage to the selected word line while performing a verify test for the memory cells connected to the selected word line in the selected sub-block.
14. The method of claim 13 , wherein:
a duration of the pre-verify voltage pulse is a function of the verify voltage.
15. The method of claim 13 , wherein:
a duration of the pre-verify voltage pulse is a function of a position of the unselected sub-block in the block and a sub-block programming order of the block.
16. The method of claim 13 , wherein:
the unselected sub-block is programmed before the selected sub-block.
17. An apparatus, comprising:
a set of memory cells arranged in NAND strings in a block, each NAND string has a drain-end and a source end, and a select gate transistor at the drain-end;
a selected word line and unselected word lines connected to the set of memory cells; and
a control circuit, the control circuit, to program memory cells connected to the selected word line in a selected sub-block of the block, is configured to:
apply a program pulse to the selected word line;
after the applying of the program pulse, increase voltages of the unselected word lines in the set of word lines to pass voltages and apply a pre-verify voltage pulse to the selected word line and to select gate transistors in an unselected sub-block of the block; and
subsequently perform a verify test for the memory cells connected to the selected word line in the selected sub-block.
18. The apparatus of claim 17 , wherein:
a duration of the pre-verify voltage pulse is a function of a data state associated with the verify test.
19. The apparatus of claim 17 , wherein:
a duration of the pre-verify voltage pulse is a function of a position of the unselected sub-block in the block and a sub-block programming order of the block.
20. The apparatus of claim 17 , wherein:
the unselected sub-block is programmed before the selected sub-block.