Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.
1. A method for fabricating a semiconductor device, comprising:
forming a vertical semiconductor fin on a semiconductor substrate;
forming an isolation layer on the semiconductor substrate, wherein the isolation layer covers a bottom portion of the vertical semiconductor fin, and wherein an active portion of the vertical semiconductor fin extends above a surface of the isolation layer;
forming a dummy gate structure to overlap a portion of the active portion of the vertical semiconductor fin, wherein the dummy gate structure comprises a sacrificial gate oxide layer, a sacrificial gate electrode layer formed on the sacrificial gate oxide layer, and a gate sidewall spacer surrounding sidewalls of the sacrificial gate electrode layer;
removing the dummy gate structure by etching the sacrificial gate electrode layer, etching the sacrificial gate oxide layer, and utilizing a first etch protection layer to prevent recessing of the isolation layer during the etching of the sacrificial gate oxide layer; and
forming a metallic gate structure in place of the dummy gate structure;
wherein removing the dummy gate structure comprises:
etching the sacrificial gate electrode layer selective to the gate sidewall spacer and the sacrificial gate oxide layer, to form a gate opening defined by the gate sidewall spacer, wherein the gate opening exposes the sacrificial gate oxide layer and a portion of the isolation layer at a bottom of the gate opening;
forming the first etch protection layer on the portion of the isolation layer exposed within the gate opening;
etching the sacrificial gate oxide layer exposed within the gate opening using an etch process which etches the sacrificial gate oxide layer selective to the first etch protection layer; and
removing the first etch protection layer using an etch process which etches the first etch protection layer selective to the isolation layer.
2. The method of claim 1 , wherein the first etch protection layer comprises silicon carbide material and wherein the isolation layer comprises silicon oxide material.
3. The method of claim 1 , wherein forming the first etch protection layer on the portion of the isolation layer exposed within the gate opening, comprises:
performing an anisotropic deposition process to selectively deposit a first layer of insulating material on exposed lateral surfaces, wherein a portion of the first layer of insulating material forms the first etch protection layer which covers the portion of the isolation layer exposed within the gate opening;
forming a second etch protection layer to cover the first etch protection layer;
performing an etch process to selectively remove portions of the first layer of insulating material which are not covered by the second etch protection layer; and
performing an etch process to remove the second etch protection layer selective to the first etch protection layer.
4. The method of claim 3 , wherein performing the anisotropic deposition process comprises anisotropically depositing a layer of silicon carbide material on the exposed lateral surfaces to form the first etch protection layer.
5. The method of claim 3 , wherein forming the second etch protection layer comprises:
forming a self-planarizing layer of insulating material to fill the gate opening with the dielectric material; and
performing an etch-back process to recess the self-planarizing layer of insulating material down to a target level which is below an upper surface of the active portion of the vertical semiconductor fin.
6. The method of claim 1 , wherein forming the dummy gate structure comprises selectively growing an oxide layer on a surface of the active portion of the vertical semiconductor fin which extends above a surface of the isolation layer, wherein sacrificial gate oxide layer comprises the selectively grown oxide layer.
7. The method of claim 1 , wherein forming the dummy gate structure comprises selectively oxidizing a surface of the active portion of the vertical semiconductor fin which extends above a surface of the isolation layer, wherein the sacrificial gate oxide layer of the dummy gate structure comprises the oxidized surface of the active portion of the vertical semiconductor fin such that removing the sacrificial gate oxide layer results in thinning of the active portion of the vertical semiconductor fin.
8. The method of claim 1 , wherein forming the vertical semiconductor fin comprises etching a surface of the semiconductor substrate to form the vertical semiconductor fin, and wherein forming the isolation layer comprises:
forming a planarized layer of oxide material over the etched surface of the semiconductor substrate to cover the vertical semiconductor fin; and
performing an etch-back process to recess the planarized layer of oxide material down to a target thickness to form the isolation layer.
9. The method of claim 1 , further comprising forming source/drain layers on exposed portions of the vertical semiconductor fin which extend past the gate sidewall spacer on opposing sides of the dummy gate structure.
10. A method for fabricating a semiconductor device, comprising:
forming a vertical semiconductor fin on a semiconductor substrate, the vertical semiconductor fin having a first width;
forming an isolation layer on the semiconductor substrate, wherein the isolation layer covers a bottom portion of the vertical semiconductor fin, and wherein an active portion of the vertical semiconductor fin extends above a surface of the isolation layer;
selectively oxidizing a surface of the active portion of the vertical semiconductor fin which extends above a surface of the isolation layer to form a sacrificial gate oxide layer;
forming a dummy gate structure to overlap a portion of the active portion of the vertical semiconductor fin, wherein the dummy gate structure comprises the sacrificial gate oxide layer, a sacrificial gate electrode layer formed on the sacrificial gate oxide layer, and a gate sidewall spacer surrounding sidewalls of the sacrificial gate electrode layer;
removing the dummy gate structure by etching the sacrificial gate electrode layer, etching the sacrificial gate oxide layer, and utilizing a first etch protection layer to prevent recessing of the isolation layer during the etching of the sacrificial gate oxide layer; and
forming a metallic gate structure in place of the dummy gate structure;
wherein removing the dummy gate structure comprises:
etching the sacrificial gate electrode layer selective to the gate sidewall spacer and the sacrificial gate oxide layer, to form a gate opening defined by the gate sidewall spacer, wherein the gate opening exposes the sacrificial gate oxide layer and a portion of the isolation layer at a bottom of the gate opening;
forming the first etch protection layer on the portion of the isolation layer exposed within the gate opening;
etching the sacrificial gate oxide layer exposed within the gate opening using an etch process which etches the sacrificial gate oxide layer selective to the first etch protection layer, wherein removing the sacrificial gate oxide layer results in thinning of the active portion of the vertical semiconductor fin within the gate opening to a second width, which is less than the first width of a portion of the vertical semiconductor fin covered by the isolation layer; and
removing the first etch protection layer using an etch process which etches the first etch protection layer selective to the isolation layer;
wherein the first etch protection layer protects the isolation layer from being recessed during etching of the sacrificial gate oxide layer so that the portion of the vertical semiconductor fin having the first width remains covered by the isolation layer.
11. The method of claim 10 , wherein the first etch protection layer comprises silicon carbide material and wherein the isolation layer comprises silicon oxide material.
12. The method of claim 10 , wherein forming the first etch protection layer on the portion of the isolation layer exposed within the gate opening, comprises:
performing an anisotropic deposition process to selectively deposit a first layer of insulating material on exposed lateral surfaces, wherein a portion of the first layer of insulating material forms the first etch protection layer which covers the portion of the isolation layer exposed within the gate opening;
forming a second etch protection layer to cover the first etch protection layer;
performing an etch process to selectively remove portions of the first layer of insulating material which are not covered by the second etch protection layer; and
performing an etch process to remove the second etch protection layer selective to the first etch protection layer.
13. The method of claim 12 , wherein performing the anisotropic deposition process comprises anisotropically depositing a layer of silicon carbide material on the exposed lateral surfaces to form the first etch protection layer.
14. The method of claim 12 , wherein forming the second etch protection layer comprises:
forming a self-planarizing layer of insulating material to fill the gate opening with the dielectric material; and
performing an etch-back process to recess the self-planarizing layer of insulating material down to a target level which is below an upper surface of the active portion of the vertical semiconductor fin.
15. The method of claim 10 , wherein forming the vertical semiconductor fin comprises etching a surface of the semiconductor substrate to form the vertical semiconductor fin, and wherein forming the isolation layer comprises:
forming a planarized layer of oxide material over the etched surface of the semiconductor substrate to cover the vertical semiconductor fin; and
performing an etch-back process to recess the planarized layer of oxide material down to a target thickness, which defines the active portion of the vertical semiconductor fin.
16. The method of claim 10 , further comprising forming source/drain layers on exposed portions of the vertical semiconductor fin which extend past the gate sidewall spacer on opposing sides of the dummy gate structure.