Redistribution layer structures for integrated circuit package
A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.
1. A method for forming an integrated circuit (IC) package, comprising:
forming a singulated IC die having a conductive via, wherein the conductive via has a peripheral edge;
coupling the singulated IC die to a carrier substrate; and
forming a routing structure having a conductive structure coupled to the conductive via, wherein the routing structure comprises:
a cap region overlapping an area of the conductive via;
a routing region having a first width from a top-down view; and
an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via and arranged to couple the cap region to the routing region, the second width being greater than the first width.
2. The method of claim 1 , further comprising:
forming a conductive through-via coupled to another conductive structure of the routing structure over the carrier substrate; and
forming a molding layer to encapsulate the singulated IC die and the conductive through-via.
3. The method of claim 1 , wherein forming the routing structure comprises forming the routing region that is non-overlapping with the conductive via.
4. The method of claim 1 , wherein forming the routing structure comprises forming the intermediate region with a first tapered region over the conductive via and a second tapered region non-overlapping with the conductive via.
5. The method of claim 1 , wherein forming the routing structure comprises forming the intermediate region with:
a first tapered region over the conductive via;
a second tapered region non-overlapping with the conductive area; and
a non-tapered region arranged to couple the first and second tapered regions.
6. The method of claim 5 , wherein the non-tapered region comprises:
a first portion over the conductive via; and
a second portion non-overlapping with the conductive area.
7. The method of claim 1 , wherein forming the routing structure comprises forming the intermediate region with a third width from the top-down view at a predetermined distance from the peripheral edge and towards the conductive via, the third width being greater than the first and second widths.
8. The method of claim 1 , wherein forming the routing structure comprises forming the intermediate region with a third width from the top-down view at a predetermined distance from the peripheral edge and away from the conductive via, the third width being greater the first width and less than the second width.
9. The method of claim 1 , wherein forming the routing structure comprises forming the intermediate region with a width within a predetermined distance from the peripheral edge greater than the first width.
10. The method of claim 9 , wherein the predetermined distance is between about 8 μm and about 12 μm.
11. The method of claim 1 , wherein the first width is between about 1 μm and about 9 μm.
12. The method of claim 1 , wherein the second width is between about 10 μm and about 70 μm.
13. A method for forming an integrated circuit (IC) package, comprising:
forming a conductive via having a peripheral edge; and
forming a redistribution layer (RDL) structure coupled to the conductive via, wherein the RDL structure comprises:
a cap region overlapping an area of the conductive via;
a routing region having a first width from a top-down view; and
an intermediate region having first and second tapered regions and arranged to couple the cap region to the routing region, the first tapered region positioned over the conductive via and the second tapered region non-overlapping with the conductive via, wherein the intermediate region has a second width from the top-down view along the peripheral edge of the conductive via, and the second width being greater than the first width.
14. The method of claim 13 , further comprising:
forming a singulated IC die having the conductive via; and
forming an insulating layer arranged to:
separate the RDL structure from the IC die; and
couple the RDL structure to the conductive via through another conductive via in the insulating layer.
15. The method of claim 13 , wherein forming the RDL structure comprises forming the routing region that is non-overlapping with the conductive via.
16. The method of claim 13 , wherein forming the RDL structure comprises forming the first tapered region with a third width from the top-down view at a predetermined distance from the peripheral edge and towards the conductive via, the third width being greater than the first and the second widths.
17. The method of claim 13 , wherein forming the RDL structure comprises forming the second tapered region with a third width from the top-down view at a predetermined distance from the peripheral edge and away from the conductive via, the third width being greater than the first width and less than the second width.
18. A method for forming an interconnect structure, comprising:
forming a conductive via having a peripheral edge; and
forming a redistribution layer (RDL) structure coupled to the conductive via, wherein the RDL structure comprises:
a cap region overlapping the conductive via;
a routing region having a first width from a top-down view and non-overlapping with the conductive via; and
an intermediate region having a first tapered region and a second tapered region and arranged to couple the cap region to the routing region, the first tapered region overlapping with the conductive via and the second tapered region non-overlapping with the conductive via, wherein the intermediate region has a second width from the top-down view along the peripheral edge of the conductive via, and the second width being greater than the first width.
19. The method of claim 18 , wherein forming the RDL structure comprises forming the first tapered region with a third width from the top-down view at a predetermined distance from the peripheral edge and towards the conductive via, the third width being greater than the first and second widths.
20. The method of claim 18 , wherein forming the RDL structure comprises forming the second tapered region with a third width from the top-down view at a predetermined distance from the peripheral edge and away from the conductive via, the third width being greater than the first width and less than the second width.