IP Library Granted Patent US 10,672,729
Granted Patent B2
US 10,672,729 · App. 15/726,260 · Granted Jun 2, 2020

Package structure and method of forming package structure

Inventors: Chih-Hsuan Tai (Taipei, TW); Ting-Ting Kuo (Hsinchu, TW); Yu-Chih Huang (Hsinchu, TW); Chih-Wei Lin (Hsinchu County, TW); Hsiu-Jen Lin (Hsinchu County, TW); Chih-Hua Chen (Hsinchu County, TW); Ming-Da Cheng (Hsinchu County, TW); Ching-Hua Hsieh (Hsinchu, TW); Hao-Yi Tsai (Hsinchu, TW); Chung-Shi Liu (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L24/02H01L21/6835H01L21/6836H01L23/3114H01L23/3135H01L24/19H01L24/96H01L24/97H01L23/3128H01L2221/6834H01L2221/68327H01L2221/68359H01L2221/68372H01L2224/02311H01L2224/02319H01L2224/02331H01L2224/02371H01L2224/02379H01L2224/02381H01L2224/12105
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Quick Facts
Patent No.
US 10,672,729
App. No.
15/726,260
Granted
Jun 2, 2020
Kind
B2
Abstract

A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.

Claims (58)

1. A method of forming a package structure, the method comprising:

disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer;

forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device;

forming a second dielectric layer over the molding compound and the semiconductor device;

forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line;

forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line;

forming a second opening in the first dielectric layer to expose the first redistribution line; and

forming a solder bump electrically connected to the first redistribution line that is in the second opening.

2. The method of claim 1 , wherein the first opening is formed by laser drilling.

3. The method of claim 1 , wherein the forming the first conductor comprises:

filling the first opening with a conductive paste; and

curing the conductive paste to form the first conductor.

4. The method of claim 1 , further comprising:

forming a second redistribution line over the second dielectric layer to electrically connect the semiconductor device and the first conductor.

5. The method of claim 1 , further comprising:

forming a third opening in the second dielectric layer to expose a conductive pad of the semiconductor device.

6. The method of claim 5 , wherein the third opening is formed by laser drilling.

7. The method of claim 5 , wherein the forming the molding compound further forms a molding compound residue over the conductive pad of the semiconductor device; and

wherein the forming the third opening removes the molding compound residue.

8. The method of claim 5 , further comprising:

forming a second conductor in the third opening.

9. The method of claim 8 , wherein the forming the second conductor comprises:

filling the third opening with a conductive paste; and

curing the conductive paste to form the second conductor.

10. The method of claim 1 , wherein the forming the molding compound comprising:

molding the semiconductor device in the molding compound with a top surface of the semiconductor device exposed.

11. A method of forming a package structure, the method comprising:

disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer;

forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, wherein a portion of the molding compound covers a conductive pad of the semiconductor device;

forming a second dielectric layer over the molding compound and the semiconductor device;

forming a first opening in the second dielectric layer and removing the portion of the molding compound to expose the conductive pad of the semiconductor device;

forming a first conductor in the first opening;

forming a second opening in the first dielectric layer to expose the first redistribution line; and

forming a solder bump electrically connected to the first redistribution line that is in the second opening.

12. The method of claim 11 , wherein the first opening is formed by laser drilling.

13. The method of claim 11 , further comprising:

forming a second redistribution line over the second dielectric layer to be electrically connected to the first conductor.

14. The method of claim 11 , further comprising:

drilling at least the first dielectric layer and the molding compound to form a third opening; and

forming a second conductor in the third opening.

15. The method of claim 11 , wherein the forming the molding compound comprising:

molding the semiconductor device in the molding compound with a top surface of the semiconductor device free from coverage of the molding compound.

16. The method of claim 11 , wherein the forming the first conductor comprises:

applying a conductive paste in the first opening; and

curing the conductive paste to form the first conductor.

17. A method of forming a package structure, the method comprising:

disposing a semiconductor device over a first dielectric layer;

forming a molding compound over the first dielectric layer and surrounding the semiconductor device;

forming a second dielectric layer over the molding compound and the semiconductor device;

forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer;

forming a conductor in the first opening such that a top surface of the conductor is higher than an interface between the second dielectric layer and the molding compound;

forming a second opening in the first dielectric layer to expose a first redistribution line in the first dielectric layer; and

forming a solder bump electrically connected to the first redistribution line that is in the second opening.

18. The method of claim 17 , wherein the conductor is formed in the first opening such that the top surface of the conductor is lower than a top surface of the second dielectric layer.

19. The method of claim 17 , further comprising:

forming a redistribution line electrically connected to the conductor, wherein an entirety of the redistribution line is above a bottom surface of the second dielectric layer.

20. The method of claim 17 , further comprising:

forming a third opening in the second dielectric layer to expose a conductive pad of the semiconductor device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: TAI, CHIH-HSUAN; KUO, TING-TING; HUANG, YU-CHIH; LIN, CHIH-WEI; LIN, HSIU-JEN; CHEN, CHIH-HUA; CHENG, MING-DA; HSIEH, CHING-HUA; TSAI, HAO-YI; LIU, CHUNG-SHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 044019/0021 →
Continuity (2)
Provisional Application 62479223 · Mar 30, 2017
Related Publication 20180286823A1 · Oct 4, 2018
Cited By (1)
US 12,489,075