Vertical field effect transistor including integrated antifuse
A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
1. A method of integrating an antifuse device with a vertical field effect transistor (FET), the method comprising:
forming a vertical semiconductor channel on an upper surface of a semiconductor substrate;
forming a split-channel gate dielectric on the outer surface of the vertical semiconductor channel;
forming an electrically conductive gate that encapsulates the split-channel gate dielectric and the vertical semiconductor channel; and
epitaxially growing a source/drain region from a first end of the vertical channel region located opposite a second end of the vertical channel region that contacts the upper surface of the semiconductor substrate,
wherein forming the split-channel gate dielectric includes forming a first dielectric layer having a first thickness and forming a second dielectric layer having a second thickness greater than the first thickness.
2. The method of claim 1 , wherein forming the split-channel gate dielectric further includes forming the first dielectric layer on an upper surface of the semiconductor substrate.
3. The method of claim 2 , wherein forming the split-channel gate dielectric further comprises forming the second dielectric layer between the first dielectric layer and the source/drain region.
4. The method of claim 1 , wherein forming the first and second dielectric layers comprises depositing the first dielectric layer having the first thickness on the outer surface of vertical semiconductor channel.
5. The method of claim 4 , wherein forming the first and second dielectric layers further comprises depositing a first electrically conductive material on an upper surface of the semiconductor substrate.
6. The method of claim 5 , wherein the first electrically conductive material encapsulates a portion of the first dielectric layer and a portion of the vertical semiconductor channel.
7. The method of claim 5 , wherein forming the first and second dielectric layers further comprises depositing the second dielectric layer directly on an upper surface of the first electrically conductive material.
8. The method of claim 7 , wherein forming the first and second layers further comprises depositing the second dielectric layer directly against an exposed portion of the first dielectric layer so as to define the second thickness.
9. The method of claim 8 , wherein forming the first and second dielectric layer further comprises depositing a second electrically conductive material on an upper surface of the first electrically conductive material to encapsulate the second dielectric layer and the vertical semiconductor channel so as to form the electrically conductive gate.
10. The method of claim 1 , wherein the first thickness defines a first dielectric breakdown strength and the second thickness defines a second dielectric breakdown strength greater than the first dielectric breakdown strength.