IP Library Granted Patent US 10,685,870
Granted Patent B2
US 10,685,870 · App. 15/897,532 · Granted Jun 16, 2020

Semiconductor device and method of manufacture

Inventors: Yao-Wen Hsu (New Taipei, TW); Ming-Che Ku (Hsinchu, TW); Neng-Jye Yang (Hsinchu, TW); Yu-Wen Wang (New Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/76814H01L21/02063H01L21/76813H01L21/76843H01L21/76877
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Quick Facts
Patent No.
US 10,685,870
App. No.
15/897,532
Granted
Jun 16, 2020
Kind
B2
Abstract

An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.

Claims (35)

1. A method of manufacturing a semiconductor device, the method comprising:

forming an opening within a first dielectric layer to expose a first conductive region and a second conductive region, the first conductive region being separated from the second conductive region by a second dielectric layer, wherein the opening comprises a via portion and a trench portion; and

reducing a surface potential difference between the first conductive region and the second conductive region.

2. The method of claim 1 , wherein the first conductive region is electrically connected to an active area of a semiconductor substrate and wherein the second conductive region is electrically isolated from the active area.

3. The method of claim 1 , wherein the reducing the surface potential difference reduces the surface potential difference to a value below an oxidation reduction potential of a material of the first conductive region.

4. The method of claim 3 , wherein the material of the first conductive region comprises copper.

5. The method of claim 1 , wherein the reducing the surface potential difference comprises applying a first treatment chemical with a conductivity of between about 0.005 μS/cm and about 40 μS·cm.

6. The method of claim 5 , wherein the first treatment chemical comprises hexane.

7. The method of claim 1 , further comprising cleaning the opening after the reducing the surface potential difference.

8. A method of manufacturing a semiconductor device, the method comprising:

forming a first via opening within a low-k dielectric layer;

forming a first trench opening within the low-k dielectric layer, wherein the forming the first trench opening extends the first via opening through the low-k dielectric layer;

applying a treatment chemical within the first via opening and the first trench opening, wherein the treatment chemical releases surface charges from within the first via opening and the first trench opening; and

performing a liner removal process after the forming the first trench opening and prior to the applying the treatment chemical.

9. The method of claim 8 , further comprising cleaning the first via opening and the first trench opening after the applying the treatment chemical.

10. The method of claim 9 , wherein the cleaning the first via opening and the first trench opening comprises applying a cleaning solution different from the treatment chemical.

11. The method of claim 10 , wherein the cleaning solution comprises:

an oxidant; and

an organic solvent.

12. The method of claim 8 , wherein the forming the first via opening forms a second via opening separated from the first via opening.

13. The method of claim 12 , wherein the first via opening exposes a conductive region electrically connected to an active area of a semiconductor substrate and wherein the second via opening exposes a conductive region electrically isolated from the active area of the semiconductor substrate.

14. A method of manufacturing a semiconductor device, the method comprising:

depositing a low-k dielectric layer over a substrate;

forming a first opening in the low-k dielectric layer;

performing a liner removal process after the forming the first opening;

applying a first treatment chemical, the first treatment chemical being volatile and having a low conductivity;

cleaning the first opening with a first cleaning solution different from the first treatment chemical, the cleaning the first opening being performed after a removal of the first treatment chemical;

after the cleaning the first opening, rinsing the first opening; and

filling the first opening with a conductive material.

15. The method of claim 14 , wherein the first treatment chemical comprises hexane.

16. The method of claim 14 , wherein the first treatment chemical comprises isopropyl alcohol.

17. The method of claim 14 , wherein the first treatment chemical comprises acetone.

18. The method of claim 14 , wherein the first cleaning solution comprises an oxidant.

19. The method of claim 14 , wherein the rinsing the first opening comprises rinsing the first opening with deionized water.

20. The method of claim 14 , wherein the first opening comprises a via portion and a trench portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2018
From: HSU, YAO-WEN; KU, MING-CHE; YANG, NENG-JYE; WANG, YU-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 044943/0909 →
Continuity (2)
Provisional Application 62551857 · Aug 30, 2017
Related Publication 20190067088A1 · Feb 28, 2019
Cited By (2)
US 12,327,793 US 12,424,556