Semiconductor device with adjustment layers and method for fabricating the same
The present application discloses a semiconductor device with adjustment layers and a method for fabricating the semiconductor device with the adjustment layers. The semiconductor device includes a substrate, an interconnection structure positioned on the substrate, a contact positioned penetrating the interconnection structure, two adjustment layers positioned on sidewalls of the contact, a contact barrier layer positioned between the interconnection structure and the contact and between the substrate and the contact, wherein the two adjustment layers are positioned between the contact and the contact barrier layer. A bottom segment of the contact barrier layer is positioned between the substrate and the contact, and bottom most points of the two adjustment layers contact the bottom portion of the contact barrier layer.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming an interconnection structure on the substrate;
forming a contact opening penetrating the interconnection structure;
conformally forming a contact barrier layer in the contact opening, wherein the contact barrier layer has two side segments and a bottom segment;
conformally forming an adjustment layer that covers an upper portion of the contact barrier layer, such that the bottom segment of the contact barrier layer is free from the adjustment layer, wherein a thickness of the adjustment layer is gradually reduced from top to bottom; and
forming a contact in the contact opening, such that the adjustment layer is formed at an upper portion of a sidewall of the contact.
2. The method for fabricating the semiconductor device of claim 1 , wherein the adjustment layer is formed of metal oxide, metal nitride, or metal carbide.
3. The method for fabricating the semiconductor device of claim 2 , wherein the step of forming the interconnection structure on the substrate comprises:
forming a first liner layer on the substrate;
forming a layer of energy-removable material on the first liner layer;
forming a second liner layer on the layer of energy-removable material; and
forming a second insulating layer on the second liner layer;
wherein the contact opening is formed penetrating the second insulating layer, the second liner layer, the layer of energy-removable material, and the first liner layer.
4. The method for fabricating the semiconductor device of claim 3 , further comprising:
performing an energy treatment to turn the layer of energy-removable material into a first insulating layer;
wherein a porosity of the first insulating layer is between about 15% and about 50%.
5. The method for fabricating the semiconductor device of claim 4 , wherein an energy source of the energy treatment is heat, light, or a combination thereof.
6. The method for fabricating the semiconductor device of claim 5 , wherein the layer of energy-removable material comprises a base material and a decomposable porogen material.
7. The method for fabricating the semiconductor device of claim 1 , wherein the adjustment layer is formed by:
conformally forming the adjustment layer on the side segments and the bottom segment of the contact barrier layer; and
performing an anisotropic etching process to remove the adjustment layer formed on the bottom segment of the contact barrier layer.
8. The method for fabricating the semiconductor device of claim 1 , further comprising:
performing a planarization process, such that a top surface of the contact barrier layer, a top surface of the adjustment layer, and a top surface of the contact are coplanar with a top surface of the interconnection structure.
9. The method for fabricating the semiconductor device of claim 3 , wherein a bottom most point of the adjustment layer at a vertical level is not lower than a vertical level of the second liner layer.