Damascene process using cap layer
A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.
1. A method of forming a semiconductor device, comprising:
forming an etch stop layer over the substrate, wherein the etch stop layer is a four-layer structure comprising, from bottom to top, AlO x N y , SiCO, AlO x and SiCO;
forming a low-k dielectric layer over etch stop layer;
forming a cap layer on the low-k dielectric layer, wherein a carbon atom content of the cap layer ranges from 20 at % to 35 at % and is greater than a carbon atom content of the low-k dielectric layer;
forming a patterned hard mask layer on the cap layer;
patterning the cap layer and the low-k dielectric layer by using the patterned hard mask layer as a mask, thereby forming an opening in the cap layer and the low-k dielectric layer; and
forming a conductive layer in the opening.
2. The method of claim 1 , further comprising:
forming a device layer between the etch stop layer and the substrate.
3. The method of claim 1 , wherein the low-k dielectric layer comprises a porous material.
4. The method of claim 1 , wherein a dielectric constant of the low-k dielectric layer is less than 3.5.
5. The method of claim 2 , wherein each layer of the four-layer structure ranges from 5 Å to 150 Å.
6. The method of claim 1 , wherein the opening is a damascene opening having a stepped sidewall in which a step is in the low-k dielectric layer.
7. The method of claim 1 , further comprising, after forming the conductive layer in the opening, polishing the conductive layer and the patterned hard mask layer by using the cap layer as a polishing stop layer.
8. The method of claim 1 , wherein the patterned hard mask layer comprises tungsten-doped carbon or TiN.
9. A method of forming semiconductor device, comprising:
forming a low-k dielectric layer over a substrate;
forming a cap layer on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer;
forming a metal-containing mask layer on the cap layer;
patterning the cap layer and the low-k dielectric layer by using the metal- containing mask layer as a mask, thereby forming an opening in the cap layer and the low-k dielectric layer; and
forming a conductive layer in the opening,
wherein the method further comprises forming a four-layer etch stop structure between the low-k dielectric layer and the substrate, wherein the opening has a lower opening and an upper opening wider than the lower opening, and the entire four-layer etch stop structure is located around a lower sidewall of the lower opening.
10. The method of claim 9 , wherein the carbon atom content of the low-k dielectric layer ranges from 10 at % to 25 at %.
11. The method of claim 9 , wherein the carbon atom content of the cap layer ranges from 20 at % to 35 at %.
12. The method of claim 9 , wherein a carbon atom content of the cap layer ranges from 25 at % to 35 at %, and a carbon atom content of the low-k dielectric layer ranges from 21 at % to 25 at %.
13. The method of claim 9 , wherein a Mohs hardness of the cap layer is higher than a Mohs hardness of the low-k dielectric layer.
14. The method of claim 9 , wherein the four-layer etch stop structure comprises, from bottom to top, a first layer, a second layer, a third layer and a fourth layer, and the second layer and the fourth layer comprise a same material.
15. The method of claim 9 , wherein a dielectric constant of the cap layer is higher than a dielectric constant of the low-k dielectric layer.
16. The method of claim 9 , wherein the cap layer is formed with a gradient carbon atom concentration in a direction away from the substrate.
17. A method of forming a semiconductor device, comprising:
forming a low-k dielectric layer over a substrate;
forming a cap layer on the low-k dielectric layer, wherein a carbon atom content of the cap layer ranges from 20 at % to 35 at % and is higher than a carbon atom content of the low-k dielectric layer;
forming a hard mask layer on the cap layer, wherein the hard mask layer comprises an oxide-based mask layer and a metal-containing mask layer on the oxide- based mask layer;
patterning the cap layer and the low-k dielectric layer by using the hard mask layer as a mask, thereby forming a damascene opening in the cap layer and the low-k dielectric layer, wherein the damascene opening has a stepped sidewall in which a step is in the low-k dielectric layer; and
forming a conductive layer in the damascene opening,
wherein the method further comprises forming a four-layer etch stop structure between the low-k dielectric layer and the substrate, wherein the damascene opening has a lower opening and an upper opening wider than the lower opening, and the entire four-layer etch stop structure is located around a lower sidewall of the lower opening.
18. The method of claim 17 , wherein the four-layer structure comprising, from bottom to top, AlO x N y , SiCO, AlO x and SiCO.
19. The method of claim 17 , wherein the cap layer is formed with a gradient carbon atom concentration in a direction away from the substrate.
20. The method of claim 17 , further comprising, after forming the conductive layer in the opening, polishing the conductive layer and the hard mask layer, until the oxide-based mask layer of the hard mask layer is exposed.