Integrated circuit package and method of fabricating the same
An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner. The redistribution circuit structure is disposed on the planar top surface of the insulating encapsulation, the top surfaces of the conductive vias and the patterned dielectric liner. The redistribution circuit structure is electrically connected to the conductive vias.
1. An integrated circuit package, comprising:
a conductive pillar;
an integrated circuit component comprising an active surface, conductive pads disposed on the active surface, a passivation layer covering the active surface, at least one alignment mark disposed on the passivation layer, and conductive vias, wherein the conductive vias are in contact with the conductive pads through contact openings of the passivation layer, the at least one alignment mark is electrically floating, the at least one alignment mark is located within a confinement of the active surface of the integrated circuit component, and the at least one alignment mark is separated from the conductive pads by the passivation layer;
a patterned dielectric liner conformally covering sidewalls of the at least one alignment mark, and sidewalls of the conductive vias;
an insulating encapsulation encapsulating the conductive pillar, sidewalls of the integrated circuit component, and the insulating encapsulation covering the patterned dielectric liner, wherein a thickness of the at least one alignment mark is less than a height of the conductive pillar; and
a fan-out redistribution circuit structure in contact with top surfaces of the insulating encapsulation, the conductive vias, the at least one alignment mark, and the conductive pillar, and the redistribution circuit structure being electrically connected to the conductive vias and the conductive pillar.
2. The integrated circuit package of claim 1 , wherein a height of the conductive vias ranges from about 5 micrometers to about 50 micrometers.
3. The integrated circuit package of claim 1 , wherein grinding marks are distributed on the first top surfaces of the conductive vias and the second top surface of the at least one alignment mark.
4. The integrated circuit package of claim 1 , wherein a minimum thickness of the patterned dielectric liner ranges from about 5 micrometers to about 10 micrometers.
5. The integrated circuit package of claim 1 , wherein the second top surface of the at least one alignment mark is in contact with a bottommost inter-dielectric layer of the redistribution circuit structure.
6. The integrated circuit package of claim 1 , wherein the first top surfaces of the conductive vias are in contact with a bottommost redistribution conductive layer of the redistribution circuit structure.
7. The integrated circuit package of claim 5 , further comprising conductive pillars embedded in and penetrating the insulating encapsulation, wherein the conductive pillars are electrically connected to the redistribution circuit structure.
8. The integrated circuit package of claim 1 , wherein the second top surface of the at least one alignment mark is substantially leveled with the first top surfaces of the conductive vias.
9. An integrated circuit package, comprising:
a conductive pillar;
an integrated circuit component comprising an active surface, conductive pads disposed on the active surface, a passivation layer covering the active surface, at least one alignment mark disposed on the passivation layer, and conductive vias, wherein the conductive vias are in contact with the conductive pads through contact openings of the passivation layer, the at least one alignment mark is electrically floating, the at least one alignment mark is located within a confinement of the active surface of the integrated circuit component, and the at least one alignment mark is separated from the conductive pads by the passivation layer;
a patterned dielectric liner conformally covering sidewalls of the at least one alignment mark, and sidewalls of the conductive vias, the patterned dielectric liner comprising a first dielectric portion and second dielectric portions connected to the first dielectric portion, the first dielectric portion covering the active surface of the integrated circuit component, and the second dielectric portions extending toward and covering the sidewalls of the conductive vias and the sidewalls of the at least one alignment mark;
an insulating encapsulation encapsulating sidewalls of the integrated circuit component, and the insulating encapsulation covering the first dielectric portion and the second dielectric portions of the patterned dielectric liner, wherein a thickness of the at least one alignment mark is less than a height of the conductive pillar; and
a redistribution circuit structure in contact with top surfaces of the insulating encapsulation, the conductive vias, the at least one alignment mark, and the conductive pillar, the redistribution circuit structure being electrically connected to the conductive vias and the conductive pillar.
10. The integrated circuit package of claim 9 , wherein the second top surface of the at least one alignment mark is in contact with a bottommost inter-dielectric layer of the redistribution circuit structure.
11. The integrated circuit package of claim 9 , wherein grinding marks are distributed on the first top surfaces of the conductive vias and the second top surface of the at least one alignment mark.
12. The integrated circuit package of claim 9 , wherein a minimum thickness of the first dielectric portion of the patterned dielectric liner ranges from about 5 micrometers to about 10 micrometers.
13. The integrated circuit package of claim 9 , wherein a top surface of each of the first dielectric portions comprises a depressed and curved surface profile.
14. The integrated circuit package of claim 9 , wherein the first top surfaces of the conductive vias are in contact with a bottommost redistribution conductive layer of the redistribution circuit structure, and the second top surface of the at least one alignment mark is in contact with a bottommost inter-dielectric layer of the redistribution circuit structure.
15. The integrated circuit package of claim 9 , wherein a height of the conductive vias ranges from about 5 micrometers to about 50 micrometers.
16. The integrated circuit package of claim 9 , wherein the second top surface of the at least one alignment mark is substantially leveled with the first top surfaces of the conductive vias.
17. A method of fabricating an integrated circuit package, the method comprising:
providing an integrated circuit component which is removably bonded to a carrier, the integrated circuit component comprising an active surface, conductive pads disposed on the active surface, a passivation layer covering the active surface, at least one alignment mark disposed on the passivation layer, conductive vias, and a dielectric layer conformally covering the active surface of the integrated circuit component, the at least one alignment mark and the conductive vias, wherein the conductive vias are in contact with the conductive pads through contact openings of the passivation layer, the at least one alignment mark is electrically floating, the at least one alignment mark is located within a confinement of the active surface of the integrated circuit component, and the at least one alignment mark is separated from the conductive pads by the passivation layer;
providing a conductive pillar on the carrier;
forming an insulating material over the carrier to encapsulate the conductive pillar, the dielectric layer formed on the integrated circuit component and sidewalls of the integrated circuit component; and
partially grinding the insulating material and the dielectric layer until the first top surfaces of the conductive vias, a second top surface of the at least one alignment mark, and a third top surface of the conductive pillar are exposed so as to respectively form an insulating encapsulation and a patterned dielectric liner, the insulating encapsulation comprising a planar top surface, the patterned dielectric liner conformally covering the active surface of the integrated circuit component and sidewalls of the conductive vias, wherein a thickness of the at least one alignment mark is less than a height of the conductive pillar.
18. The method of claim 17 , wherein the dielectric layer is formed by a coating or dispensing process followed by a curing process.
19. The method of claim 17 , wherein a minimum thickness of the patterned dielectric liner ranges from about 5 micrometers to about 10 micrometers.
20. The method of claim 17 further comprising:
forming a redistribution circuit structure on the planar top surface of the insulating encapsulation, the first top surfaces of the conductive vias, the second top surface of the at least one alignment mark and the patterned dielectric liner, the redistribution circuit structure being electrically connected to the conductive vias; and
after forming the redistribution circuit structure, de-bonding the integrated circuit component and the insulating encapsulation from the carrier.