Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
1. An integrated circuit structure, comprising:
a first N-type fin-FET device having a first fin, the first N-type fin-FET device comprising a first gate electrode having a first layer having a composition, the first layer having a first thickness vertically over a top of the first fin; and
a second N-type fin-FET device having a second fin, the second N-type fin-FET device comprising a second gate electrode having a second layer having the composition, the second layer having a second thickness vertically over a top of the second fin, the second thickness greater than the first thickness, wherein the second gate electrode of the second N-type fin-FET device has a gate length greater than a gate length of the first gate electrode of the first N-type fin-FET device.
2. The integrated circuit structure of claim 1 , wherein the first N-type fin-FET device is a logic transistor, and the second N-type fin-FET device is an I/O transistor.
3. The integrated circuit structure of claim 1 , further comprising:
a first gate dielectric between the first fin and the first gate electrode; and
a second gate dielectric between the second fin and the second gate electrode.
4. The integrated circuit structure of claim 3 , wherein the first and second gate dielectrics comprise hafnium and oxygen.
5. The integrated circuit structure of claim 1 , wherein the first and second layers comprise aluminum.
6. The integrated circuit structure of claim 1 , wherein the first and second layers comprise titanium.
7. The integrated circuit structure of claim 1 , wherein the first and second layers comprise a metal carbide.
8. An integrated circuit structure, comprising:
a first P-type fin-FET device having a first fin, the first P-type fin-FET device comprising a first gate electrode having a first layer having a composition, the first layer having a first thickness vertically over a top of the first fin; and
a second P-type fin-FET device having a second fin, the second P-type fin-FET device comprising a second gate electrode having a second layer having the composition, the second layer having a second thickness vertically over a top of the second fin, the second thickness greater than the first thickness, wherein the second gate electrode of the second P-type fin-FET device has a gate length greater than a gate length of the first gate electrode of the first P-type fin-FET device.
9. The integrated circuit structure of claim 8 , wherein the first P-type fin-FET device is a logic transistor, and the second P-type fin-FET device is an I/O transistor.
10. The integrated circuit structure of claim 8 , further comprising:
a first gate dielectric between the first fin and the first gate electrode; and
a second gate dielectric between the second fin and the second gate electrode.
11. The integrated circuit structure of claim 10 , wherein the first and second gate dielectrics comprise hafnium and oxygen.
12. The integrated circuit structure of claim 8 , wherein the first and second layers comprise aluminum.
13. The integrated circuit structure of claim 8 , wherein the first and second layers comprise titanium.
14. The integrated circuit structure of claim 8 , wherein the first and second layers comprise a metal carbide.
15. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first N-type fin-FET device having a first fin, the first N-type fin-FET device comprising a first gate electrode having a first layer having a composition, the first layer having a first thickness vertically over a top of the first fin; and
a second N-type fin-FET device having a second fin, the second N-type fin-FET device comprising a second gate electrode having a second layer having the composition, the second layer having a second thickness vertically over a top of the second fin, the second thickness greater than the first thickness, wherein the second gate electrode of the second N-type fin-FET device has a gate length greater than a gate length of the first gate electrode of the first N-type fin-FET device.
16. The computing device of claim 15 , further comprising:
a memory coupled to the board.
17. The computing device of claim 15 , further comprising:
a communication chip coupled to the board.
18. The computing device of claim 15 , further comprising:
a camera coupled to the board.
19. The computing device of claim 15 , further comprising:
a battery coupled to the board.
20. The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.