Gate-all-around field effect transistors with air-gap inner spacers and methods
Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.
1. A semiconductor structure comprising:
a semiconductor substrate; and
a transistor on the substrate, the transistor comprising:
source/drain regions;
a stack of semiconductor nanoshapes extending laterally between the source/drain regions;
a gate wrapping around a center portion of each nanoshape;
a gate sidewall spacer positioned laterally adjacent to external sidewalls of the gate, wherein end portions of each nanoshape extend laterally beyond internal sidewalls of the gate through the gate sidewall spacer to the source/drain regions; and
air-gap inner spacers, wherein each air-gap inner spacer comprises:
a pair of vertical air-gap sections within the gate sidewall spacer on opposing sides of the stack at an end adjacent to a source/drain region; and
horizontal air-gap sections below the nanoshapes, respectively, and extending laterally between the pair of vertical air-gap sections, wherein the horizontal air-gap sections are between the source/drain region and an internal sidewall of the gate.
2. The semiconductor structure of claim 1 , wherein the nanoshapes comprise any of nanowires and nanosheets.
3. The semiconductor structure of claim 1 , wherein each air-gap inner spacer comprises an inner spacer cavity and a dielectric liner that lines surfaces of the nanoshapes, the gate, and the gate sidewall spacer within the inner spacer cavity.
4. The semiconductor structure of claim 3 , wherein the dielectric liner comprises silicon nitride.
5. The semiconductor structure of claim 1 , wherein tops of the vertical air-gap sections of each air-gap inner spacer are above a level of a top surface of an uppermost nanoshape in the stack and further above a level of top surfaces of the source/drain regions.
6. The semiconductor structure of claim 1 , wherein a proximal side of each source/drain region abutting the nanoshapes is essentially planar.
7. The semiconductor structure of claim 1 , further comprising a buried insulator between the semiconductor substrate and the transistor, wherein the source/drain regions and the gate are above and immediately adjacent to the buried insulator.