Nonvolatile semiconductor storage device with cell transistors
A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.
1. A nonvolatile semiconductor storage device comprising:
a first pair of cell transistors sharing a first node connected to one of a bit line and a source line, wherein the first pair of cell transistors forms a first pair of mask read only memory cells;
a second pair of cell transistors sharing a second node connected to the one of the bit line and the source line, wherein the second pair of cell transistors forms a second pair of mask read only memory cells;
transistor gate lines connected to the first pair of cell transistors and the second pair of cell transistors, respectively;
a dummy transistor arranged between the first pair of cell transistors and the second pair of cell transistors; and
a dummy gate line laid in parallel with the transistor gate lines, wherein
the dummy gate line is connected to the dummy transistor, and
the dummy gate line applies an off voltage to the dummy transistor.
2. The nonvolatile semiconductor storage device according to claim 1 , wherein
an interval between the transistor gate lines connected to the first pair of cell transistors is equal to an interval between the dummy gate line and one of the transistor gate lines neighboring the dummy gate line.
3. The nonvolatile semiconductor storage device according to claim 1 , wherein
a plurality of impurity diffusion layers corresponding to the first node and second nodes of the first pair of cell transistors are formed at equal intervals in a continuous active region.
4. The nonvolatile semiconductor storage device according to claim 3 , wherein
the dummy transistor includes one linear active region ranging on both sides of the dummy gate line without a break.
5. The nonvolatile semiconductor storage device according to claim 1 , wherein
data is written to each of the first pair of cell transistors and the second pair of cell transistors by a contact type of mask programming.
6. The nonvolatile semiconductor storage device according to claim 5 , wherein
presence or absence of connection of second nodes of the first pair of cell transistors and the second pair of cell transistors to other of the bit line and the source line is set according to the data, respectively.
7. The nonvolatile semiconductor storage device according to claim 6 , wherein
the presence or absence of connection of the second nodes of the first pair of cell transistors and the second pair of cell transistors to the other of the bit line and the source line is set by one of presence or absence of a contact, presence or absence of a via or a through hole, or presence or absence of a metal according to the data.
8. The nonvolatile semiconductor storage device according to claim 1 , wherein
each of the first pair of cell transistors and the second pair of cell transistors is a negative-channel metal oxide semiconductor field-effect transistor.
9. The nonvolatile semiconductor storage device according to claim 1 , further comprising:
an X-decoder configured to drive the transistor gate lines;
a Y-decoder configured to drive the bit line;
a sense amplifier configured to read data via the bit line; and
a controller configured to control each part of the nonvolatile semiconductor storage device.
10. An electronic apparatus comprising the nonvolatile semiconductor storage device according to claim 1 .
11. The nonvolatile semiconductor storage device according to claim 2 , wherein
one of the first pair of cell transistors neighboring the dummy transistor includes an impurity diffusion layer, and
the dummy transistor includes an impurity diffusion layer continuously formed with the impurity diffusion layer of the one of the first pair of cell transistors neighboring the dummy transistor.
12. A nonvolatile semiconductor storage device comprising:
a first pair of cell transistors;
first transistor gate lines connected to the first pair of cell transistors, respectively;
a dummy transistor next to the first pair of cell transistors; and
a dummy gate line laid in parallel with the first transistor gate lines, wherein
the dummy gate line is connected to the dummy transistor,
the dummy gate line applies an off voltage to the dummy transistor, and
an interval between the first transistor gate lines is equal to an interval between the dummy gate line and one of the first transistor gate lines neighboring the dummy gate line.
13. The nonvolatile semiconductor storage device according to claim 12 further comprising:
a second pair of cell transistors next to the dummy transistor on an opposite side of the first pair of cell transistors; and
second transistor gate lines connected to the second pair of cell transistors, respectively, wherein
an interval between the second transistor gate lines is equal to an interval between the dummy gate line and one of the second transistor gate lines neighboring the dummy gate line.
14. The nonvolatile semiconductor storage device according to claim 12 , wherein the first pair of cell transistors forms a pair of mask read only memory cells.
15. A nonvolatile semiconductor storage device comprising:
a first cell transistor;
a second cell transistor;
transistor gate lines connected to the first cell transistor and the second cell transistor, respectively;
a dummy transistor arranged between the first cell transistor and the second cell transistor; and
a dummy gate line laid in parallel with the transistor gate lines, wherein
the dummy gate line applies an off voltage to the dummy transistor,
the first cell transistor includes an impurity diffusion layer,
the dummy transistor includes an impurity diffusion layer continuously formed with the impurity diffusion layer of the first cell transistor, and
the second cell transistor includes an impurity diffusion layer, and
the dummy transistor further includes an impurity diffusion layer continuously formed with the impurity diffusion layer of the second cell transistor.
16. The nonvolatile semiconductor storage device according to claim 15 , wherein
the dummy transistor further includes one linear active region ranging on both sides of the dummy gate line without a break.
17. The nonvolatile semiconductor storage device according to claim 15 , wherein
the first cell transistor forms a first mask read only memory cell, and
the second cell transistor forms a second mask read only memory cell.