Granted Patent B2

US 12,475,293 · App. 17/891,760 · Granted Nov 18, 2025

Inventors: Panjae Park (Seoul, KR); Yoonjin Kim (Yeosu-si, KR); Kwanyoung Chun (Suwon-si, KR)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

G06F30/392G06F30/394H01L23/5286

Abstract

Claims (104)

1 . A cell comprising individual source regions, the cell comprising:

active regions extending in a first direction and being spaced apart from each other in a second direction different from the first direction;

gate lines extending across the active regions in the second direction and being spaced apart from each other in the first direction;

first contacts arranged on both sides of each of the gate lines in the first direction and connected to the active regions;

metal lines arranged over the gate lines and the first contacts, the metal lines extending in the first direction and being spaced apart from each other in the second direction;

second contacts connecting the gate lines to the metal lines; and

vias connecting the first contacts to the metal lines,

wherein two gate lines of the gate lines adjacent to each other in the first direction comprise a first interval or a second interval greater than the first interval therebetween, and

wherein a source isolation structure extending in the second direction is provided between the two gate lines adjacent to each other at the second interval, and an individual source region respectively corresponding to the two gate lines through the source isolation structure is provided in the active regions.

2 . The cell of claim 1 ,

wherein the cell comprises a first outer portion and a second outer portion;

wherein the cell is separated from other adjacent cells through a single diffusion break (SDB) structure provided on both the first outer portion and the second outer portion of the cell in the first direction,

wherein the source isolation structure is spaced a distance apart from each of the two gate lines, the distance being substantially identical to the first interval, and

wherein the source isolation structure comprises the SDB structure.

3 . The cell of claim 1 , wherein the individual source region is connected to a power line or a ground line from among the metal lines through a corresponding first contact and a corresponding via.

4 . The cell of claim 1 , wherein the cell is a standard cell in which any of four inverters, four NANDs, or four NORs are connected to one another in a parallel structure.

5 . The cell of claim 4 ,

wherein the active regions comprise a first active region, which is provided at a high position in the second direction, and a second active region, which is provided at a low position in the second direction,

wherein the metal lines comprise a power line, which is provided at a top position in the second direction, a ground line, which is provided at a bottom position in the second direction, and intermediate lines between the power line and the ground line,

wherein the first active region comprises a p-type metal-oxide semiconductor (PMOS) transistor and is connected to the power line and the intermediate lines through the first contacts and the vias, and

wherein the second active region comprises an n-type metal-oxide semiconductor (NMOS) transistor and is connected to the ground line and the intermediate lines through the first contacts and the vias.

6 . The cell of claim 1 ,

wherein the cell is a standard cell comprising inverters,

wherein the active regions comprise a first active region, which is provided at a high position in the second direction, and a second active region, which is provided at a low position in the second direction,

wherein each of four gate lines extends across the first active region and the second active region,

wherein the source isolation structure is provided between a second gate line and a third gate line from the left in the first direction and separates each of the first active region and the second active region into two regions,

wherein the cell comprises a line-symmetric structure around the source isolation structure,

wherein the first contacts are respectively arranged in the first active region and the second active region on the left side of a first gate line from the left in the first direction, and between the second gate line and the source isolation structure, and

wherein the first contacts are arranged in the first active region and the second active region between the first gate line and the second gate line from the left in the first direction.

7 . The cell of claim 6 ,

wherein the metal lines comprise:

a power line, which is provided at a top position in the second direction,

a ground line, which is provided at a bottom position in the second direction, and

intermediate lines provided between the power line and the ground line,

wherein contacts of the first contacts arranged only in the first active region are connected to the power line through the vias,

wherein contacts of the first contacts arranged only in the second active region are connected to the ground line through the via,

wherein contacts of the first contacts arranged in the first active region and the second active region are connected to the intermediate lines through the vias, and

wherein the first active region comprises a p-type metal-oxide semiconductor (PMOS) transistor and the second active region comprises an n-type metal-oxide semiconductor (NMOS) transistor.

8 . The cell of claim 1 ,

wherein the cell is a standard cell comprising NANDs,

wherein the active regions comprise a first active region, which is provided at a high position in the second direction, and a second active region, which is provided at a low position in the second direction,

wherein each of eight gate lines extends across the first active region and the second active region,

wherein the source isolation structure is provided between a second gate line and a third gate line and between a sixth gate line and a seventh gate line from the left in the first direction, the source isolation structure separating each of the first active region and the second active region into three regions,

wherein the cell comprises a line-symmetric structure around contacts of the first contacts arranged in the first active region and the second active region between a fourth gate line and a fifth gate line from the left in the first direction,

wherein the first contacts are respectively arranged in the first active region and the second active region on the left side of a first gate line, between the first gate line and the second gate line, and between the second gate line and the source isolation structure, from the left in the first direction,

wherein a contact provided in the second active region on the left side of the first gate line from the left in the first direction is connected to a contact provided in the first active region on the right side through the vias and the metal lines, and

wherein a contact provided in the first active region on the left side of the fourth gate line from the left in the first direction is connected to a contact provided in the second active region on the right side through the vias and the metal lines.

9 . The cell of claim 8 ,

wherein the metal lines comprise:

a power line, which is provided at a top position in the second direction,

a ground line, which is provided at a bottom position in the second direction, and

intermediate lines provided between the power line and the ground line,

wherein the first contacts arranged in the first active region on the left side of the first gate line from the left in the first direction and both sides of the source isolation structure are connected to the power line through the vias,

wherein the first contacts arranged in the second active region on both sides of the source isolation structure from the left in the first direction are connected to the ground line through the vias, and

wherein the first active region comprises a p-type metal-oxide semiconductor (PMOS) transistor and the second active region comprises an n-type metal-oxide semiconductor (NMOS) transistor.

10 . The cell of claim 1 ,

wherein the cell is a standard cell comprising NORs,

wherein the metal lines comprise:

a power line, which is provided at a top position in the second direction,

a ground line, which is provided at a bottom position in the second direction, and

intermediate lines provided between the power line and the ground line, and

wherein the active regions, the gate lines, the first contacts, the second contacts, and the vias of the cell comprise mirror-symmetric structures with respect to the active regions, gate lines, first contacts, second contacts, and vias of a NAND cell in the second direction.

11 . The cell of claim 1 , wherein the active regions comprise any one of a planar field effect transistor (FET), a fin-FET, and a multi-bridge channel (MBC) FET.

12 . An integrated circuit, comprising:

cells arranged in a first direction and a second direction different from the first direction,

wherein each of the cells comprises:

active regions extending in the first direction and being spaced apart from each other in the second direction;

gate lines extending across the active regions in the second direction and being spaced apart from each other in the first direction;

first contacts arranged on both sides of each of the gate lines in the first direction and connected to the active regions;

metal lines arranged over the gate lines and the first contacts, the metal lines extending in the first direction and being spaced apart from each other in the second direction;

second contacts connecting the gate lines to the metal lines; and

vias connecting the first contacts to the metal lines,

wherein two gate lines of the gate lines adjacent to each other in the first direction comprise a first interval or a second interval greater than the first interval therebetween, and

wherein a source isolation structure extending in the second direction is provided between the two gate lines adjacent to each other at the second interval, and an individual source region respectively corresponding to the two gate lines through the source isolation structure is provided in the active regions.

13 . The integrated circuit of claim 12 ,

wherein each cell of the cells comprise a first outer portion and a second outer portion;

wherein each cell of the cells is separated from other adjacent cells through a single diffusion break (SDB) structure provided on both the first outer portion and the second outer portion in the first direction,

wherein the source isolation structure is spaced a distance apart from each of the two gate lines, the distance being substantially identical to the first interval, and

wherein the source isolation structure comprises the SDB structure.

14 . The integrated circuit of claim 12 , wherein the individual source region is connected to a power line or a ground line from among the metal lines through a corresponding first contact and a corresponding via.

15 . The integrated circuit of claim 12 , wherein each cell is a standard cell in which any of four inverters, four NANDs, or four NORs are connected to one another in a parallel structure.

16 . The integrated circuit of claim 15 ,

wherein the active regions comprise a first active region, which is provided at a high position in the second direction, and a second active region, which is provided at a low position in the second direction,

wherein the metal lines comprise a power line, which is provided at a top position in the second direction, a ground line, which is provided at a bottom position in the second direction, and intermediate lines provided between the power line and the ground line,

wherein the first active region comprises a p-type metal-oxide semiconductor (PMOS) transistor and is connected to the power line and the intermediate lines through the first contacts and the vias, and

wherein the second active region comprises an n-type metal-oxide semiconductor (NMOS) transistor and is connected to the ground line and the intermediate lines through the first contacts and the vias.

17 . An integrated circuit comprising

cells arranged in a first direction and a second direction different from the first direction, wherein the cells are separated from each other in the first direction by a single diffusion break (SDB) structure,

wherein each of the cells comprises:

a first active region and a second active region extending in the first direction and being spaced apart from each other in the second direction;

gate lines extending across the first active region and the second active region in the second direction and being spaced apart from each other in the first direction; and

metal lines arranged over the gate lines, extending in the first direction, and being spaced apart from each other in the second direction,

wherein two gate lines of the gate lines adjacent to each other in the first direction comprise a first interval or a second interval twice the first interval therebetween, and

wherein a source isolation structure extending in the second direction is provided between the two gate lines adjacent to each other at the second interval, and an individual source region respectively corresponding to the two gate lines through the source isolation structure is formed in the first active region and the second active region.

18 . The integrated circuit of claim 17 ,

wherein the source isolation structure is spaced a distance apart from each of the two gate lines, the distance being substantially identical to the first interval, and

wherein the source isolation structure comprising the SDB structure.

19 . The integrated circuit of claim 17 ,

wherein the individual source region comprises a first individual source region provided in the first active region and a second individual source region provided in the second active region,

wherein the first individual source region is connected to a power line from among the metal lines through first contacts and vias, and

wherein the second individual source region is connected to a ground line from among the metal lines through the first contacts and the vias.

20 . The integrated circuit of claim 17 ,

wherein the first active region and the second active region comprise any one of a planar field effect transistor (FET), a fin FET, and a multi-bridge channel (MBC) FET, and

wherein each cell of the cells is a standard cell in which any of four inverters, four NANDs, or four NORs are connected to one another in a parallel structure.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (24)