Integrated 1T1R RRAM memory cell

1. An apparatus comprising:

a bipolar junction transistor (BJT) comprising a base contact, a base region, a collector contact, a collector region and an integrated emitter contact; and

an integrated resistive element comprising a resistive layer disposed proximate an integrated electrode layer, the integrated resistive element positioned between the base region and the integrated emitter contact such that at least a portion of the resistive layer is disposed proximate the base region and at least a portion of the integrated electrode layer is disposed proximate the integrated emitter contact.

2. The apparatus of claim 1 , wherein the resistive layer comprises a plurality of sub-layers.

3. The apparatus of claim 1 , wherein the resistive layer comprises an oxide material or a chalcogenide material.

4. The apparatus of claim 1 , wherein the integrated electrode is formed of a conductive or a semi-conductive material.

5. The apparatus of claim 1 , wherein the resistive layer comprises an oxide material selected from the group comprising one or more of HfOx (hafnium oxide), TaOx (tantalum oxide), WOx (tungsten oxide), TiOx (titanium oxide), SiOx (silicon oxide), AlOx (aluminum oxide) and/or alloys and/or combinations thereof, or the resistive layer comprises a chalcogenide material selected from the group comprising S (sulfur), Se (selenium), Te (tellurium), GeTe (germanium tellurium) and SiTe (silicon tellurium) and/or alloys and/or combinations thereof.

6. The apparatus of claim 1 , wherein at least one of the base region and/or collector region comprises one or more of group III-V elements.

7. The apparatus of claim 1 , wherein at least one of the base region and/or the collector region comprises a group IV element.

8. The apparatus of claim 1 , wherein the integrated electrode is to interact with the resistive layer in response to a first applied bias voltage to create a conductive path between the integrated electrode and the base region or in response to a second applied bias voltage to break the conductive path between the integrated electrode and the base region.

9. The apparatus of claim 1 , wherein a width W E of the integrated electrode is in the range of 2 nanometers (nm) to 10 nm, a width W R of the resistive layer is in the range of 2 nm to 10 nm, a width W C of the collector region is less than 10 nm and a width W B of the base region is in the range of 1 nm to 25 nm and is less than a carrier diffusion length.

10. A system comprising:

a processor;

a memory controller; and

a memory array, the memory array comprising a plurality of memory cells, each memory cell comprising:

a bipolar junction transistor (BJT) comprising a base contact, a base region, a collector contact, a collector region and an integrated emitter contact; and

an integrated resistive element comprising a resistive layer and an integrated electrode, the resistive element positioned between the base region and the integrated emitter contact.

11. The system of claim 10 , wherein the resistive layer comprises a plurality of sub-layers.

12. The system of claim 10 , wherein the resistive layer comprises an oxide material or a chalcogenide material.

13. The system of claim 10 , wherein the integrated electrode is formed of a conductive or a semi-conductive material.

14. The system of claim 10 , wherein the resistive layer comprises an oxide material selected from the group comprising one or more of HfOx (hafnium oxide), TaOx (tantalum oxide), WOx (tungsten oxide), TiOx (titanium oxide), SiOx (silicon oxide), AlOx (aluminum oxide) and/or alloys and/or combinations thereof, or the resistive layer comprises a chalcogenide material selected from the group comprising S (sulfur), Se (selenium), Te (tellurium), GeTe (germanium tellurium) and SiTe (silicon tellurium) and/or alloys and/or combinations thereof.

15. The system of claim 10 , wherein the integrated electrode is to interact with the resistive layer in response to a first applied bias voltage to create a conductive path between the integrated electrode and the base region or in response to a second applied bias voltage to break the conductive path between the integrated electrode and the base region.

16. The system of claim 10 , wherein each memory cell further comprises a metal oxide semiconductor field effect transistor (“MOS transistor”) coupled to the integrated emitter contact, the MOS transistor to reduce a leakage current when an associated memory cell is not selected.

17. The system of claim 10 , wherein the memory array further comprises a current limiting transistor coupled to the word line, a subset of the plurality of memory cells coupled to the word line.

18. A memory array comprising:

a word line, a bit line and a selector line; and

a plurality of memory cells, each memory cell comprising:

a bipolar junction transistor (BJT) comprising a base contact, a base region, a collector contact, a collector region and an integrated emitter contact; and

an integrated resistive element comprising a resistive layer and an integrated electrode, the resistive element positioned between the base region and the integrated emitter contact.

19. The memory array of claim 18 , wherein the resistive layer comprises a plurality of sub-layers.

20. The memory array of claim 18 , wherein the resistive layer comprises an oxide material or a chalcogenide material.

21. The memory array of claim 18 , wherein the integrated electrode is formed of a conductive or a semi-conductive material.

22. The memory array of claim 18 , wherein the resistive layer comprises an oxide material selected from the group comprising one or more of HfOx (hafnium oxide), TaOx (tantalum oxide), WOx (tungsten oxide), TiOx (titanium oxide), SiOx (silicon oxide), AlOx (aluminum oxide) and/or alloys and/or combinations thereof, or the resistive layer comprises a chalcogenide material selected from the group comprising S (sulfur), Se (selenium), Te (tellurium), GeTe (germanium tellurium) and SiTe (silicon tellurium) and/or alloys and/or combinations thereof.

23. The memory array of claim 18 , wherein the integrated electrode is to interact with the resistive layer in response to a first applied bias voltage to create a conductive path between the integrated electrode and the base region or in response to a second applied bias voltage to break the conductive path between the integrated electrode and the base region.

24. The memory array of claim 18 , wherein each memory cell further comprises a metal oxide semiconductor field effect transistor (“MOS transistor”) coupled to the integrated emitter contact, the MOS transistor to reduce a leakage current when an associated memory cell is not selected.

25. The memory array of claim 18 , wherein the memory array further comprises a current limiting transistor coupled to the word line, a subset of the plurality of memory cells coupled to the word line.