IP Library Granted Patent US 10,707,146
Granted Patent B2
US 10,707,146 · App. 16/088,532 · Granted Jul 7, 2020

Semiconductor device and method for manufacturing same, for releaved stress and high heat conductivity

Inventors: Motoru Yoshida (Tokyo, JP); Yoshiyuki Suehiro (Tokyo, JP); Kazuyuki Sugahara (Tokyo, JP); Yosuke Nakanishi (Tokyo, JP); Yoshinori Yokoyama (Tokyo, JP); Shinnosuke Soda (Tokyo, JP); Komei Hayashi (Tokyo, JP)
Assignee: MITSUBISHI ELECTRIC CORPORATION
H01L23/40H01L21/52H01L21/56H01L23/3736H01L25/07H01L25/18H01L2224/32225
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Quick Facts
Patent No.
US 10,707,146
App. No.
16/088,532
Granted
Jul 7, 2020
Kind
B2
Abstract

Provided is a semiconductor device having high heat conductivity and high productivity. A semiconductor device includes an insulating substrate, a semiconductor element, a die-bond material, a joining material, and a cooler. The insulating substrate has an insulating ceramic, a first conductive plates disposed on one surface of the insulating ceramic, and a second conductive plate disposed on another surface of the insulating ceramic. The semiconductor element is disposed on the first conductive plate through the die-bond material. The die-bond material contains sintered metal. The semiconductor element has a bending strength degree of 700 MPa or more, and has a thickness of 0.05 mm or more and 0.1 mm or less. The cooler is joined to the second conductive plate through the joining material.

Claims (22)

1. A semiconductor device comprising:

an insulating substrate comprising an insulating plate, a first conductive plate disposed on one surface of the insulating plate, and a second conductive plate disposed on another surface of the insulating plate;

a sintered metal;

a semiconductor element disposed on the first conductive plate through the sintered metal, the semiconductor element having a crack-proceeding depth rate of 30% or less of a chip thickness, and having a thickness of 0.05 mm or more and 0.1 mm or less;

a joining material; and

a cooler joined to the second conductive plate through the joining material.

2. The semiconductor device according to claim 1 , wherein the sintered metal has a thickness of 3 μm or more and 100 μm or less.

3. The semiconductor device according to claim 2 , wherein the semiconductor element comprises a semiconductor base made of SiC.

4. The semiconductor device according to claim 1 , wherein the insulating plate is made of silicon nitride, aluminum nitride, or alumina.

5. The semiconductor device according to claim 4 , wherein the semiconductor element comprises a semiconductor base made of SiC.

6. The semiconductor device according to claim 1 , wherein the second conductive plate comprises a stacked structure of copper or an alloy of copper, and aluminum or an alloy of aluminum.

7. The semiconductor device according to claim 6 , wherein the semiconductor element comprises a semiconductor base made of SiC.

8. The semiconductor device according to claim 1 , wherein the cooler is made of aluminum or an alloy of aluminum.

9. The semiconductor device according to claim 8 , wherein the semiconductor element comprises a semiconductor base made of SiC.

10. The semiconductor device according to claim 1 , wherein the semiconductor element comprises a semiconductor base made of SiC.

11. A method for manufacturing a semiconductor device, comprising:

(a) preparing an insulating substrate comprising an insulating plate, a first conductive plate disposed on one surface of the insulating plate, and a second conductive plate disposed on another surface of the insulating plate;

(b) disposing a semiconductor element to the first conductive plate through a sintered metal, the semiconductor element having a thickness of 0.05 mm or more and 0.1 mm or less, and having a crack-proceeding depth rate of 30% or less of the thickness; and

(c) joining a cooler to the second conductive plate through a first joining material.

12. The method for manufacturing a semiconductor device according to claim 11 , further comprising:

(d) joining, through a second joining material, a lead to the semiconductor element on a side that is opposite to a side on which the sintered metal is disposed, and

(e) sealing the semiconductor element, the insulating substrate, and the lead with a sealing resin.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2018
From: YOSHIDA, MOTORU; SUEHIRO, YOSHIYUKI; SUGAHARA, KAZUYUKI; NAKANISHI, YOSUKE; YOKOYAMA, YOSHINORI; SODA, SHINNOSUKE; HAYASHI, KOMEI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 046976/0290 →
Priority Claims (1)
JP 2016-085068 · Apr 21, 2016 · national
Continuity (1)
Related Publication 20190122955A1 · Apr 25, 2019