Method of forming semicondcutor device package
A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.
1. A structure, comprising:
a semiconductor die;
a semiconductor package;
a warpage adjusting component disposed on a back surface of the semiconductor package; and
an encapsulating material encapsulating the semiconductor die, the semiconductor package, and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material.
2. The structure as claimed in claim 1 further comprising a redistribution structure, wherein the semiconductor die and the semiconductor package are disposed on and electrically connected to the redistribution structure, and the redistribution structure is covered by the encapsulating material.
3. The structure as claimed in claim 2 further comprising:
first connectors disposed between the redistribution structure and the semiconductor die;
second connectors disposed between the redistribution structure and the semiconductor package; and
an underfill encapsulating the first and second connectors, wherein the underfill is encapsulated by the encapsulating material.
4. The structure as claimed in claim 3 , wherein the underfill is in contact with sidewalls of the semiconductor die and sidewalls of the semiconductor package.
5. The structure as claimed in claim 1 , wherein a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.
6. The structure as claimed in claim 1 , wherein the semiconductor die is a system on chip (SOC), and the semiconductor package is a dynamic random access memory (DRAM) chip-scale package (CSP).
7. The structure as claimed in claim 1 , wherein the warpage adjusting component is attached to the back surface of the second semiconductor devices through a die attach film.
8. The structure as claimed in claim 1 , wherein a thickness of the semiconductor die is greater than a thickness of each of the semiconductor package.
9. A structure, comprising:
a redistribution structure;
a semiconductor die disposed on the redistribution structure;
semiconductor packages disposed on the redistribution structure, wherein the semiconductor die being electrically connected to the semiconductor dies through the redistribution structure;
a warpage adjusting component attached to back surfaces of the semiconductor packages; and
an encapsulating material encapsulating the semiconductor die and the semiconductor package, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material.
10. The structure as claimed in claim 9 , wherein a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.
11. The structure as claimed in claim 9 , wherein the warpage adjusting component is a warpage adjusting frame attached to the back surfaces of the semiconductor packages.
12. The structure as claimed in claim 11 , wherein the warpage adjusting frame is further attached to a back surface of the semiconductor die.
13. The structure as claimed in claim 9 , wherein the warpage adjusting frame comprises an aperture exposing the back surface of the semiconductor die and the back surfaces of the semiconductor packages.
14. The structure as claimed in claim 9 , wherein the warpage adjusting frame comprises a first aperture exposing the back surface of the semiconductor die and second apertures exposing the back surfaces of the semiconductor packages.
15. The structure as claimed in claim 9 , wherein the warpage adjusting frame is attached to the encapsulating material, the back surface of the semiconductor die, and the back surfaces of the semiconductor packages though an adhesive.
16. The structure as claimed in claim 9 further comprising:
first connectors disposed between the redistribution structure and the semiconductor die;
second connectors disposed between the redistribution structure and the semiconductor packages; and
an underfill encapsulating the first and second connectors, wherein the underfill is encapsulated by the encapsulating material.
17. The structure as claimed in claim 16 , wherein the underfill is in contact with sidewalls of the semiconductor die and sidewalls of the semiconductor packages.
18. A structure, comprising:
a redistribution structure;
a first semiconductor device and second semiconductor devices disposed on in side-by-side manner, the first semiconductor device being surrounded by the second semiconductor devices, the first semiconductor device and the second semiconductor devices being electrically connected to the redistribution structure;
an encapsulating material at least encapsulating the semiconductor die and the semiconductor package, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material; and
at least one warpage adjusting component attached the semiconductor die and the semiconductor package encapsulated by the encapsulating material.
19. The structure as claimed in claim 18 , wherein the at least one warpage adjusting component is embedded in the encapsulating material and attached to back surfaces of the second semiconductor devices through die attach films.
20. The structure as claimed in claim 18 , wherein the at least one warpage adjusting component is disposed over a surface of the encapsulating material and is attached to back surfaces of the second semiconductor devices through an adhesive.