Memory device for supporting command bus training mode and method of operating the same
There are provided, a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.
1. A memory device for supporting a command bus training (CBT) mode, the memory device comprising:
a data clock signal;
command/address signals comprising a CBT pattern;
data signals including a first data signal and second data signals, the second data signals being in one-to-one correspondence with the command/address signals from which the CBT pattern is output in the CBT mode; and
a control logic configured to initiate entry into the CBT mode in response to a first logic level of the first data signal synchronized with the data clock signal and further configured to exit from the CBT mode in response to a second logic level opposite to the first logic level of the first data signal.
2. The memory device of claim 1 , wherein the control logic is further configured to receive the CBT pattern through first terminals associated with the command/address signals, and to output the CBT pattern through second terminals associated with the second data signals in the CBT mode.
3. The memory device of claim 1 , wherein the control logic is further configured to receive a reference voltage setting code through terminals associated with the second data signals and, to change a reference voltage value in accordance with a reference voltage setting code in the CBT mode.
4. The memory device of claim 3 , wherein the control logic is further configured to compare the changed reference voltage value with a voltage level of each of the command/address signals.
5. The memory device of claim 1 , further comprising a mode register configured to store an on-die termination (ODT) code of the command/address signals, an ODT code of the data signals, or an ODT code of a pair of data clock signals.
6. The memory device of claim 5 , wherein the control logic is further configured to terminate a line of each of the command/address signals to a respective resistance value corresponding to setting of an ODT code of the respective command/address signals in the CBT mode.
7. The memory device of claim 6 , wherein the control logic is further configured to set an ODT code of the command/address signals in relation to a frequency set point operation mode signal based on an operation frequency of the memory device in the CBT mode.
8. The memory device of claim 5 , wherein the control logic is further configured to turn off ODT in a data bus to which the data signals are transmitted in the CBT mode.
9. The memory device of claim 5 , wherein the control logic is further configured to terminate a data bus through which the data signals are transmitted to a resistance value corresponding to setting of an ODT code of the data signals in a normal mode in which a writing or reading operation of the memory device is performed.
10. The memory device of claim 5 , wherein the control logic is further configured to terminate a line of each of the pair of data clock signals to a resistance value corresponding to setting of an ODT code of the pair of data clock signals.
11. A method of operating a memory device for supporting a command bus training (CBT) mode, the method comprising:
receiving a data clock signal;
entering the CBT mode in response to a first logic level of a first data signal synchronized with the data clock signal;
receiving a CBT pattern formed of a bit configuration of command/address signals in the CBT mode;
outputting the CBT pattern through terminals associated with second data signals, which are in one-to-one correspondence with the command/address signals, in the CBT mode; and
exiting from the CBT mode in response to a second logic level opposite to the first logic level of the first data signal synchronized with the data clock signal,
wherein the second data signals do not comprise the first data signal in the CBT mode.
12. The method of claim 11 , further comprising receiving a reference voltage setting code through terminals associated with the second data signals and changing a reference voltage value in accordance with the reference voltage setting code in the CBT mode.
13. The method of claim 12 , further comprising comparing the changed reference voltage value with a voltage level of each of the command/address signals.
14. The method of claim 11 , further comprising storing an ODT code of the command/address signals, an ODT code of the data signals, or an ODT code of a pair of data clock signals in a mode register.
15. The method of claim 14 , further comprising terminating a line associated with each of the command/address signals to a respective resistance value corresponding to setting of an ODT code of the respective command/address signals in the CBT mode.
16. The method of claim 15 , wherein setting of the ODT code of the command/address signals comprises:
setting the ODT code of the respective command/address signals responsive to a frequency set point operation mode signal based on an operation frequency of the memory device.
17. The method of claim 14 , further comprising turning off ODT in a data bus through which the data signals are transmitted in the CBT mode.
18. The method of claim 14 , further comprising terminating a data bus through which the data signals are transmitted to a resistance value corresponding to an ODT code setting of the data signals in a normal mode in which a writing or reading operation of the memory device is performed.
19. The method of claim 14 , further comprising terminating a line of each of the pair of data clock signals to a resistance value corresponding to an ODT code setting of the pair of data clock signals in the CBT mode.
20. A memory system comprising:
a memory device configured to enter a command bus training (CBT) mode or exit from the CBT mode in response to a logic level of a first data signal; and
a memory controller configured to transmit a CBT pattern to the memory device through terminals associated with command/address signals,
wherein second data signals for outputting the CBT pattern in the CBT mode are in one-to-one correspondence with the command/address signals and do not comprise the first data signal in the CBT mode, and
wherein the memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an ODT code setting stored in a mode register, and to turn off ODT of the data signals in the CBT mode.