Memory device for supporting command bus training mode and method of operating the same
There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.
1. A method of operating a memory device, the method comprising:
receiving a clock signal through a clock terminal;
receiving a data clock signal through a data clock terminal;
receiving a frequency set point (FSP) change command through a command/address (CA) bus, an operating frequency of the memory device being switched based on the FSP change command;
receiving a first data signal through a first data terminal;
detecting a logic level of the first data signal at one of a rising edge and a falling edge of the data clock signal, and entering into a command bus training (CBT) mode upon detecting a first logic level of the first data signal; and
switching parameters of FSP operation settings based on the FSP change command during the CBT mode,
wherein the parameters of the FSP operation settings includes a first FSP operation mode signal representing a low frequency setting in a normal mode, a second FSP operation mode signal representing an intermediate frequency setting in the normal mode, and a third FSP operation mode signal representing a high frequency setting in the normal mode.
2. The method of claim 1 , wherein the receiving of the FSP change command comprises receiving a mode register setting command configured to change the parameters of the FSP operation settings of a mode register.
3. The method of claim 2 , wherein the switching of the FSP operation settings based on the FSP change command during the CBT mode comprises:
setting the parameters of the FSP operation settings in the mode register according to the FSP change command; and
operating the CBT with a FSP selected by the setting of the parameters of the FSP operation mode signal in the mode register.
4. The method of claim 3 , further comprising:
operating the normal mode with the selected FSP.
5. The method of claim 1 , wherein the first FSP operation mode signal is a default parameter of the FSP operation settings.
6. The method of claim 1 , further comprising:
setting a command/address on-die termination (CA ODT) code in a mode register; and
determining a termination resistance value of the CA bus during the CBT mode according to the setting of the CA ODT code.
7. The method of claim 1 , further comprising:
setting a data clock on-die termination (WCK ODT) code in a mode register; and
determining a termination resistance value of the data clock signal during the CBT mode according to the setting of the WCK ODT code.
8. The method of claim 1 , further comprising:
setting a data on-die termination (DQ ODT) code in a mode register; and
determining a termination resistance value of data terminals including the first data terminal during the normal mode according to the setting of the DQ ODT code.
9. The method of claim 8 , further comprising:
turning off the determining of the termination resistance value of the data terminals during the CBT mode.
10. The method of claim 1 , further comprising:
changing a level of a reference voltage during the CBT mode, the reference voltage being compared with a CBT pattern received during the CBT mode.
11. The method of claim 1 , further comprising:
exiting the CBT mode upon determining a second logic level of the first data signal, the second logic level being opposite to the first logic level.