Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive word line layers located over a substrate;

a plurality of vertical memory strings, wherein each vertical memory string comprises a series connection of a memory stack structure and a selector element; and

bit lines that are laterally spaced apart along a first horizontal direction, laterally extend along a second horizontal direction, and are electrically connected to top ends of the vertical memory strings,

wherein:

each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel;

each of the selector elements comprises a two terminal device that is configured to provide at least two different resistivity states;

each of the selector elements is located between the alternating stack and the bit lines; and

dummy word lines are located between the selector elements and the electrically conductive word line layers.

2. The three-dimensional memory device of claim 1 , wherein:

each of the selector elements comprises a vertical stack of a bottom electrode, a memory element, and a top electrode;

the top electrode is electrically connected to one of the bit lines; and

the bottom electrode is electrically connected to a respective one of the vertical semiconductor channels through a respective drain region.

3. The three-dimensional memory device of claim 2 , wherein the respective drain region contacts the bottom electrode and the respective one of the vertical semiconductor channels.

4. The three-dimensional memory device of claim 2 , wherein the memory element comprises a vacancy-modulated memory element.

5. The three-dimensional memory device of claim 2 , wherein the memory element comprises a conductive-bridge memory element.

6. The three-dimensional memory device of claim 2 , wherein the memory element comprises a phase change memory element.

7. The three-dimensional memory device of claim 2 , wherein the memory element comprises a spin-torque-transfer (STT) magnetic memory element containing a magnetic tunneling junction.

8. The three-dimensional memory device of claim 2 , wherein the selector element has a pillar structure.

9. The three-dimensional memory device of claim 2 , wherein:

the top electrode of the selector element and the bottom electrode of the selector element laterally extend along different horizontal directions; and

the memory element is located within an overlap area between the top electrode and the bottom electrode.

10. The three-dimensional memory device of claim 1 , wherein:

each of the memory stack structures is located within a respective memory opening that vertically extends through the alternating stack; and

each memory film comprises a stack including a respective blocking dielectric, a respective set of charge storage elements, and a respective tunneling dielectric.

11. The three-dimensional memory device of claim 1 , wherein:

each vertical memory string comprises a series connection of a memory stack structure and a selector device; and

the selector device comprises a series connection of a select transistor and the selector element.

12. A method of operating the three-dimensional memory device of claim 1 , comprising:

activating a first group of vertical memory strings by setting each selector element within the first group to a low resistivity state and deactivating a second group of vertical memory strings by setting each selector element within the second group to a high resistivity state; and

performing an operation selected from programming or reading least one memory element within the first group of vertical memory strings while the second group of vertical memory strings remains deactivated.

13. The method of claim 12 , further comprising deactivating the first group of vertical memory strings by setting each selector element within the first group of vertical memory strings to the high resistivity state after the programming or reading operation.

14. The method of claim 13 , further comprising:

activating the first and the second groups of vertical memory strings by setting each selector element within the first and second groups of vertical memory strings to the low resistivity state;

performing an erase operation on the first and second groups of vertical memory strings; and

deactivating the first and second groups of vertical memory strings by setting each selector element within the first and second groups of vertical memory strings to the high resistivity state after the erase operation.