IP Library › Granted Patent US 10,734,389
Granted Patent B2
US 10,734,389 · App. 16/596,165 · Granted Aug 4, 2020

Semiconductor device and method for fabricating the same

Inventors: Jeong-Yeop Lee (Gyeonggi-do, KR); Dong-Su Park (Gyeonggi-do, KR); Jong-Bum Park (Seoul, KR); Sang-Do Lee (Gyeonggi-do, KR); Jae-Min Lee (Seoul, KR); Kee-Jeung Lee (Seoul, KR); Jun-Soo Jang (Chungcheongbuk-do, KR)
Assignee: SK hynix Inc.
H01L27/10855H01L27/10814H01L27/10852H01L27/10876H01L27/10894H01L28/75H01L28/91H01L28/92
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Quick Facts
Patent No.
US 10,734,389
App. No.
16/596,165
Granted
Aug 4, 2020
Kind
B2
Abstract

A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Claims (15)

1. A semiconductor device, comprising:

a hybrid pillar-type bottom electrode including a cylindrical first bottom electrode and a pillar-type second bottom electrode filling a cylindrical inside of the cylindrical first bottom electrode;

a supporter suitable for supporting an outer wall of the hybrid pillar-type bottom electrode;

a dielectric layer formed over the hybrid pillar-type bottom electrode and the supporter; and

a top electrode disposed over the dielectric layer,

wherein the pillar-type second bottom electrode includes:

a conductive pillar body filling the cylindrical inside of the first bottom electrode; and

a conductive pillar head extending from the conductive pillar body to cover an upper surface of the cylindrical first bottom electrode,

wherein the supporter is in direct contact with a sidewall of the pillar head and an upper sidewall of the cylindrical first bottom electrode.

2. The semiconductor device of claim 1 , wherein an upper surface of the supporter and an upper surface of the conductive pillar head are disposed at the same level.

3. The semiconductor device of claim 1 , wherein the conductive pillar head has a greater width than that of the pillar body.

4. The semiconductor device of claim 1 , wherein the conductive pillar head and the pillar body are made of the same material.

5. The semiconductor device of claim 1 , wherein the conductive pillar head and the pillar body are made of polysilicon.

6. The semiconductor device of claim 1 , wherein the cylindrical first bottom electrode comprises a different material than the pillar-type second bottom electrode.

7. The semiconductor device of claim 1 , wherein the cylindrical first bottom electrode includes a metal or a metal nitride, and the pillar-type second bottom electrode includes polysilicon.

Priority Claims (1)
KR 10-2017-0049286 · Apr 17, 2017 · national
Continuity (3)
Continuation 16234181 · Dec 27, 2018
Continuation 15865710 · Jan 9, 2018
Related Publication 20200043933A1 · Feb 6, 2020
Cited By (1)
US 12,557,308