IP Library Granted Patent US 10,734,496
Granted Patent B2
US 10,734,496 · App. 16/177,368 · Granted Aug 4, 2020

Semiconductor device and method for fabricating the same

Inventors: Yi-Fan Li (Tainan, TW); Wen-Yen Huang (Changhua County, TW); Shih-Min Chou (Tainan, TW); Zhen Wu (Kaohsiung, TW); Nien-Ting Ho (Tainan, TW); Chih-Chiang Wu (Tainan, TW); Ti-Bin Chen (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/4966H01L27/092H01L29/401
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Quick Facts
Patent No.
US 10,734,496
App. No.
16/177,368
Granted
Aug 4, 2020
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.

Claims (22)

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first region and a second region;

forming a first bottom barrier metal (BBM) layer on the first region and the second region;

forming a first work function metal layer on the first BBM layer on the first region and the second region;

removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and

forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.

2. The method of claim 1 , further comprising:

forming a gate structure on the substrate on the first region and the second region;

forming an inter-layer dielectric (ILD) layer around the gate structure;

removing the gate structure to form a recess;

forming the first BBM layer in the recess;

forming the first WFM layer on the first BBM layer;

removing the first WFM layer and part of the first BBM layer on the second region;

forming the diffusion barrier layer on the first region and the second region;

forming a second WFM layer on the diffusion barrier layer; and

forming a low resistance metal layer on the second WFM layer to form a metal gate.

3. The method of claim 2 , further comprising forming the diffusion barrier layer on a top surface and a sidewall of the first WFM layer.

4. The method of claim 2 , wherein the first WFM layer comprises a p-type WFM layer and the second WFM layer comprises a n-type WFM layer.

5. The method of claim 1 , wherein a thickness of the first BBM layer on the first region is equal to a combined thickness of the first BBM layer and the diffusion barrier layer on the second region.

6. The method of claim 1 , wherein the first BBM layer and the diffusion barrier layer comprise a same material.

7. The method of claim 1 , further comprising forming a second BBM layer on the substrate before forming the first BBM layer.

8. The method of claim 7 , wherein the first BBM layer and the second BBM layer comprise different materials.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: UNITED MICROELECTRONICS CORP.
To: STELLAR SEMICONDUCTOR JAPAN GK
Reel/Frame 071913/0125 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2018
From: LI, YI-FAN; HUANG, WEN-YEN; CHOU, SHIH-MIN; WU, ZHEN; HO, NIEN-TING; WU, CHIH-CHIANG; CHEN, TI-BIN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 047375/0422 →
Priority Claims (1)
TW 107134933 A · Oct 3, 2018 · national
Continuity (1)
Related Publication 20200111884A1 · Apr 9, 2020