Memory device with compensation for erase speed variations due to blocking oxide layer thinning
Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.
1. An apparatus, comprising:
a plurality of memory cells arranged in NAND strings in a plurality of sub-blocks of a block, the NAND strings comprise a plurality of concentric layers, the concentric layers comprise a blocking oxide layer, a thickness of the blocking oxide layer is different in different sub-blocks of the plurality of sub-blocks, and each NAND string comprises a channel; and
a control circuit, the control circuit is configured to, in an erase operation for the block, charge up channels of NAND strings in the plurality of sub-blocks, including charging up channels of NAND strings in a central sub-block among the plurality of sub-blocks to a higher voltage than a voltage to which channels of NAND strings in one edge sub-block among the plurality of sub-blocks are charged up.
2. The apparatus of claim 1 , wherein:
the NAND strings comprise a first select gate transistor at a drain-end of the NAND strings; and
the control circuit, to charge up the channels of the NAND strings in the central sub-block, is configured to apply a control gate voltage to the first select gate transistors in the NAND strings in the central sub-block and, to charge up the channels of the NAND strings in the one edge sub-block, is configured to apply a control gate voltage to the first select gate transistors in the NAND strings in the one edge sub-block which is higher than the control gate voltage applied to the first select gate transistors in the NAND strings in the central sub-block.
3. The apparatus of claim 2 , wherein:
each NAND string comprises a second select gate transistor adjacent to the first select gate transistor; and
during the charge up of the channels of the NAND strings in the central sub-block, the control circuit is configured to apply a common control gate voltage to the second select gate transistors in the one edge sub-block and in the central sub-block.
4. The apparatus of claim 1 , wherein:
the NAND strings comprise a first select gate transistor at a drain-end of the NAND strings and a second select gate transistor adjacent to the first select gate transistor;
during the charge up of the channels of the NAND strings in the central sub-block, the control circuit is configured to apply a control gate voltage to the second select gate transistors in the central sub-block; and
during the charge up of the channels of the NAND strings in the one edge sub-block, the control circuit is configured to apply a control gate voltage to the second select gate transistors in the one edge sub-block which is higher than the control gate voltage applied to the second select gate transistors in the central sub-block.
5. The apparatus of claim 4 , wherein:
the charging up of the channels of the NAND strings in the plurality of sub-blocks occurs in a plurality of erase loops;
the control gate voltage applied to the second select gate transistors in the NAND strings in the one edge sub-block is stepped up in the plurality of erase loops by a first step size; and
the control gate voltage applied to the second select gate transistors in the NAND strings in the central sub-block is stepped up in the plurality of erase loops by a second step size which is lower than the first step size.
6. The apparatus of claim 1 , wherein:
the NAND strings comprise a first select gate transistor at a drain-end of the NAND strings and a second select gate transistor adjacent to the first transistor;
in each NAND string, a control gate of the second select gate transistor is disconnected from a control gate of the first select gate transistor;
the control gates of the first select gate transistors in the one edge sub-block are connected to the control gates of the first select gate transistors in the central sub-block; and
the control circuit is configured to, during the charging up of the channels of the NAND strings in the plurality of sub-blocks, apply a common control gate voltage to the first select gate transistors in the one edge sub-block and to the first select gate transistors in the central sub-block for generating gate-induced drain leakage at the first select gate transistors in the one edge sub-block and at the first select gate transistors in the central sub-blocks, respectively, and apply a control gate voltage to the second select gate transistors in the one edge sub-block which is higher than a control gate voltage applied to the second select gate transistors in the central sub-block.
7. The apparatus of claim 6 , wherein:
after the charging up of the channels of the NAND strings in the plurality of sub-blocks, the control circuit is configured to determine one or more sub-blocks which have passed an erase-verify test and one or more sub-blocks which have not passed the erase-verify test and, in response to the determination, continue the erase operation for the one or more sub-blocks which have not passed the erase-verify test while inhibiting a further erasing of the one or more sub-blocks which have passed the erase-verify test.
8. The apparatus of claim 1 , wherein:
the NAND strings comprise a first select gate transistor at a drain-end of the NAND strings;
a pair of the sub-blocks have equal erase speeds; and
control gates of the first select gate transistors in the pair of the sub-blocks having equal erase speeds are connected to one another.
9. The apparatus of claim 8 , wherein:
the control circuit is configured to, in the erase operation for the block, charge up channels of NAND strings in the pair of the sub-blocks having the equal erase speed to a same voltage.
10. The apparatus of claim 1 , wherein:
a thickness of the blocking oxide layer is less in the one edge sub-block than in the central sub-block.
11. The apparatus of claim 1 , wherein:
the one edge sub-block comprises multiple rows of NAND strings including one row and another row;
an edge of the block is closer to the one row than to the another row; and
the control circuit is configured to, in the erase operation, charge up channels of NAND strings in the another row by a greater amount than an amount to which NAND strings in the one row are charged up.
12. The apparatus of claim 11 , wherein:
the control circuit, to charge up the channels of the NAND strings in the another row by the greater amount than the amount to which the NAND strings in the one row are charged up, is configured to apply an erase voltage to drain ends of the NAND strings in the another row which is higher than an erase voltage which is applied concurrently to drain ends of the NAND strings in the one row.
13. The apparatus of claim 12 , wherein:
the multiple rows of NAND strings in the one edge sub-block each comprise a first select gate transistor at a drain-end of the multiple rows of NAND strings; and
control gates of the first select gate transistors are connected to one another.
14. The apparatus of claim 11 , wherein:
a thickness of the blocking oxide layer is less in the one row than in the another row.
15. The apparatus of claim 1 , wherein:
to charge up the channels of NAND strings in the plurality of sub-blocks, the control circuit is configured to apply a common erase voltage to the drain ends of the NAND strings in the plurality of sub-blocks.
16. A method, comprising:
applying a common erase voltage to bit lines connected to drain ends of NAND strings in a plurality of sub-blocks of a block, wherein the plurality of sub-blocks comprise a central sub-block and an edge sub-block and the NAND strings comprise one or more select gate transistors at the drain ends of the NAND strings; and
during the applying of the common erase voltage, applying control gate voltages to one or more select gate transistors at the drain ends of the NAND strings in the edge sub-block which are greater than control gate voltages applied to one or more select gate transistors at the drain ends of the NAND strings in the central sub-block.
17. The method of claim 16 , wherein:
the NAND strings comprise a plurality of concentric layers;
the concentric layers comprise a blocking oxide layer;
a thickness of the blocking oxide layer is different in different sub-blocks of the plurality of sub-blocks; and
the control gate voltages are applied to the one or more select gate transistors at the drain ends of the NAND strings in each sub-block according to a thickness of the blocking oxide layer.
18. An apparatus, comprising:
a plurality of memory cells arranged in NAND strings in a plurality of sub-blocks of a block, each NAND string comprises a channel, wherein each of the NAND strings comprises a blocking oxide layer, and a thickness of the blocking oxide layer is different in different sub-blocks of the plurality of sub-blocks; and
a control circuit, the control circuit is configured to, in an erase operation for the block, charge up channels of the NAND strings in each sub-block according to a thickness of the blocking oxide layer in each sub-block.
19. The apparatus of claim 18 , wherein:
the control circuit, to charge up the channels of the NAND strings in each sub-block, is configured to generate an amount of gate-induced drain leakage at select gate transistors of the NAND strings in each sub-block according to a position of each sub-block in the block.